Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.     

Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs

This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were used for the fabrication of p/sup +/-Si/sub 1-x/Ge/sub x//n-Si heterojunctions. In the first approach, high dose Ge ion implantation followed by boron implantation into Si was used to form very shallow p/sup +/-Si/sub 1-x/Ge/sub x//n-Si junctions (x/spl les/0.2). In the second approach, thin Ge films were deposited onto Si substrates by conventional low pressure chemical vapor deposition. This was followed by boron implantation into the Ge and thermal annealing to co-diffuse Ge and B atoms into Si and form p/sup +//n heterojunctions. The electrical characteristics of the heterojunction diodes were comparable to those of conventional Si (homo) junctions. Secondary ion mass spectrometry (SIMS) concentration-depth profiles indicate that dopant segregation in the Si/sub 1-x/Ge/sub x/ regions resulted in the formation of ultra-shallow and abrupt junctions that could be used as S/D extensions for sub-100 nm CMOS generations. PMOS transistors fabricated using these techniques exhibit superior short-channel performance compared to control devices, for physical gate lengths down to 60 nm.     

Light emission near 1.3 /spl mu/m using ITO-Al/sub 2/O/sub 3/-Si/sub 0.3/Ge/sub 0.7/-Si tunnel diodes

We have fabricated Sn : In/sub 2/O/sub 3/ (ITO)-Al/sub 2/O/sub 3/ dielectric on Si/sub 1-x/Ge/sub x/-Si metal-oxide-semiconductor tunnel diodes which emit light at around 1.3 /spl mu/m, for x=0.7. The emitted photon energy is smaller than the bandgap energy of Si, thus, avoiding strong light absorption by the Si substrate. The optical device structure is compatible with that of a metal-oxide-semiconductor field-effect transistor, since a conventional doped poly-Si gate electrode will be transparent to the emitted light. Increasing the Ge composition from 0.3 to 0.4 only slightly decreases the light-emitting efficiency.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

Gate Influence on the Layout Sensitivity of $ hbox{Si}_{1 - x}hbox{Ge}_{x} hbox{S/D}$ and $hbox{Si}_{1 - y}hbox{C}_{y} hbox{S/D}$ Transistors Including an Analytical Model

We present a simulation study on the effect of the gate module on the channel stress in Si_1-xGe_x and Si_1-yC_y S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si_1-xGe_x and Si_1-yC_y S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si_1-xGe_x/Si_1-yC_y S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si_1-xGe_x/Si_1-yC_y S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si_1-xGe_x and Si_1-yC_y S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers

Dual-work-function metal gates fabricated by full silicidation (FUSI) of Co-Ni bi-layer with doped poly-Si were investigated for the first time, along with single-metal FUSI systems of CoSi/sub 2/ and NiSi. Complete conversion of poly-Si into Co-Ni alloy silicided metal gate (FUSI) Co/sub x/Ni/sub 1-x/Si/sub 2/ was demonstrated. Although a linear relationship between work function and Ni percentage was observed for FUSI of undoped poly-Si systems, the work functions of doped Co/sub x/Ni/sub 1-x/Si/sub 2/ are almost identical to those of doped NiSi FUSI metal gates. The alloy FUSI metal gates explored in this letter provide a new class of metal gates for CMOS devices that combine the advantages of both NiSi and CoSi/sub 2/, i.e., proper work function tunability of NiSi and high thermal stability of CoSi/sub 2/.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

Performance improvement in tensile-strained In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As metamorphic HEMT

This paper proposes a In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As (x=0.3-0.5-0.3) metamorphic high-electron mobility transistor with tensile-strained channel. The tensile-strained channel structure exhibits significant improvements in dc and RF characteristics, including extrinsic transconductance, current driving capability, thermal stability, unity-gain cutoff frequency, maximum oscillation frequency, output power, power gain, and power added efficiency.     

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.