SER-Tvpack:基于软错误率评估的SRAM型FPGA的装箱算法

为了提高基于SRAM的FPGA(SFPGA)上的容软错误能力,提出了一种基于软错误率(soft error rate,SER)评估的装箱算法SER-Tvpack.通过结合软错误率的两个组成部分错误传播率(error propagation probability,EPP)和节点错误率(node error rate,NER),得到软错误评估标准SER的估算值,并将该值作为可靠性因子加入到代价函数中指导装箱过程,以减少装箱后可编程逻辑块(configuration logic block,CLB)之间互连的软错误率,从而提高设计的可靠性.对20个MCNC基准电路(最大基准电路集)进行实验,结果表明,与基准时序装箱算法T-Vpack及已有的容错装箱算法FTvpack相比较,软故障率分别减少了14.5%和4.11%.而且,与F-Tvpack比较,在仅增加0.04%的面积开销下,减少了2.31%的关键路径的时延,提供了较好的时序性能.     

降低寄存器软错误的静态寄存器重分配方法

针对寄存器交换方法在降低寄存器软错误率过程中,未考虑寄存器分配过程对软错误所带来影响的问题,提出一种基于活跃变量对于软错误影响的静态寄存器重分配方法。首先,引入活跃变量权值来评估其对寄存器软错误的影响;然后,提出两条规则,在进行寄存器交换后对活跃变量进行寄存器的重新分配。该方法在更小粒度的活跃变量层次,进一步降低了寄存器软错误率。实验和分析表明,相对于寄存器交换方法,该策略能进一步降低30%的寄存器软错误率,增强了寄存器的可靠性。     

利用SIMD向量化的数据流软错误检测算法

由于现代处理器不断缩减芯片上元件尺寸、速度不断提高，会导致严重的可靠性问题.针对现有基于冗余的数据流软检错算法效率低下问题，本文提出一种基于SIMD向量化的数据流软错误检测算法VBSED,利用单指令多数据流并行性来提高软件冗余算法的效率，将原代码与冗余代码转换为高效率的SIMD代码，生成具有检错能力的加固程序.对比实验结果表明本文提出的算法可降低加固代码的时空开销，该算法还具有现有算法一般不能检测缓存等部件软错误的优点，并通过故障注入实验验证本文算法在寄存器、缓存和主存部件具有更高的错误检错率.     

多级缓存模式下的数据块替换优化算法

多数处理器中采用多级包含的cache存储层次,现有的末级cache块替换算法带来的性能开销较大.针对该问题,提出一种优化的末级cache块替换算法PLI,在选择丢弃块时考虑其在上级cache的访问频率,以较小的代价选出最优的LLC替换块.在时钟精确模拟器上的评测结果表明,该算法较原算法性能平均提升7％.     

抗单粒子翻转的低功耗锁存器设计

随着CMOS工艺缩减至纳米尺寸,锁存器对空间辐射环境中高能粒子引起的软错误越发敏感.为缓解软错误对锁存器电路的影响,提出一种基于45 nm CMOS工艺的单粒子翻转自恢复的低功耗锁存器.该锁存器使用3个C单元构成内部互锁的结构,每个C单元的输出节点的状态由另2个C单元的输出节点决定;任意C单元的输出节点发生单粒子翻转后,该锁存器将通过内部互锁的反馈路径将翻转节点恢复正确;在瞬态脉冲消散后没有节点处于高阻态,提出的锁存器适用于采用了时钟门控技术的低功耗电路.大量的SPICE仿真结果表明,与已有的加固锁存器相比,文中提出的锁存器在延时、功耗、面积开销和软错误加固能力上取得了良好的平衡,平均节省57.53%的面积-功耗-延时积开销;详尽的蒙特卡洛仿真实验表明,该锁存器对工艺、供电电压和温度的波动不敏感.     

基于SRAM结构的FPGA抗辐射布局算法

分析由辐射造成的单粒子翻转(SEU)软错误,在通用布局布线工具的基础上,提出一种基于SRAM结构的现场可编程门阵列 (FPGA)抗辐射布局算法。该算法通过优化电路单元在FPGA中的布局位置,减少布线资源开路敏感错误、短路敏感错误以及SEU敏感点的数目。测试结果表明,该算法能减少SEU软错误,提高FPGA的抗辐射性能,并且无需增加额外的设计成本和硬件开销。     

一种容软错误的BIST结构

针对深亚微米工艺下瞬态故障引发的软错误可能成为芯片失效的重要原因,提出一种容软错误的BIST结构--FT-CBILBO.该结构对并发内建逻辑块观察器进行改进,通过对多输入特征寄存器进行功能复用,构建双模冗余的容错微结构,并且能有效地降低开销;在触发器输出端插入C单元,可有效地针对单事件翻转进行防护,阻塞瞬态故障引发的软错误.在UMC 0.18μm工艺下的实验结果表明,FT-CBILBO面积开销为28.37%～33.29%,性能开销为4.99%～18.20%.     

位宽感知的寄存器绑定算法

寄存器绑定是高层次综合中的一个基础优化问题,主要目标是在保证电路功能的同时最小化寄存器资源的使用.传统的方法尝试将编译器的寄存器分配算法应用于寄存器绑定中,但却忽略了分配问题与绑定问题的差异性,因此在绑定过程中引入了额外的资源约束,或采用了不适合电路设计的编译优化技巧,从而导致资源浪费.为了解决这些问题, 本文将寄存器绑定问题转化为连续多重着色问题,并提出了一种基于位宽与顶点度结合的启发式求解方法.该方法通过对变量的位宽和活跃区间等信息的细粒度刻画和建模,能够进一步优化寄存器资源的开销,同时无需插入额外的指令.我们将该算法与两种典型算法进行了比较,实验结果表明, 我们的算法在Mibench测试集的96.72%的测试用例中达到了理论最优解,比其他两种方法分别提高了31.5%和25.1%;在Rosetta测试集的所有测试用例中均表现为最优解,比其他两种方法分别提高了7.41%和7.39%.     

MIMO信号检测中的可靠性约束算法研究

为在较低复杂度的情况下提升误码率的检测性能,提出一种基于QR分解的低复杂度的可靠性约束算法。采用阴影面积约束方法判断软估计的可靠性,同时引入星座点作为候选点,从多个候选点中选出最优候选点进行反馈。仿真结果表明,与常规的QR分解算法相比,该算法只需增加较小的算法复杂度即可明显改善系统存在的干扰,并且在判决回馈中减少错误传播。同时,可以通过约束阈值的大小和候选点数量控制运算复杂度并改善算法的误码率检测性能。     

65nm工艺下单粒子加固锁存器设计

随着工艺尺寸的缩减,单粒子引发的软错误成为威胁电路可靠性的重要原因.基于SMIC 65 nm CMOS工艺,提出一种单粒子加固锁存器设计.首先针对单粒子翻转,使用具有状态保持功能的C单元,并且级联成两级;然后针对单粒子瞬态,将延迟单元嵌入在锁存器内部并与级联C单元构成时间冗余;最后选择基于施密特触发器的电路作为延迟单元.实验结果表明,相比已有的加固设计,该锁存器不存在共模故障敏感节点,还能容忍时钟电路中的单粒子瞬态;版图面积、功耗和时钟电路功耗分别平均下降30.58%,44.53%和26.51%;且该锁存器的功耗对工艺、供电电压和温度的波动不敏感.     

Using Tag-Match Comparators for Detecting Soft Errors

Soft errors caused by high energy particle strikes are becoming an increasingly important problem in microprocessor design. With increasing transistor density and die sizes, soft errors are expected to be a larger problem in the near future. Recovering from these unexpected faults may be possible by reexecuting some part of the program only if the error can be detected. Therefore it is important to come up with new techniques to detect soft errors and increase the number of errors that are detected. Modern microprocessors employ out-of-order execution and dynamic scheduling logic. Comparator circuits, which are used to keep track of data dependencies, are usually idle. In this paper, we propose various schemes to exploit on-chip comparators to detect transient faults. Our results show that around 50% of the errors on the wakeup logic can be detected with minimal hardware overhead by using the proposed techniques.     

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Radiation-induced single bit upsets (SBUs) and multi-bit upsets (MBUs) are more prominent in Field Programmable Gate Arrays (FPGAs) due to the presence of a large number of latches in the configuration memory (CM) of FPGAs. At the same time, SBUs and MBUs in the CM can permanently or temporarily affect the hardware circuit implemented on FPGA. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from permanent faults arising due to such SBUs and MBUs. Different existing techniques used to mitigate the effect of soft errors in FPGA have high overhead and their implementations are also quite complex. In this paper, we have proposed efficient single bit as well as multi-bit error correcting methods to correct errors in the CM of FPGAs using simple parity equations and Erasure code. These codes are easy to implement, and the needed decoding circuits are also simple. Use of Dynamic Partial Reconfiguration (DPR) along with a simple hardware scheduling algorithm based download manager helps to perform the error correction in the CM without suspending the operations of the other hardware blocks. We propose a first of its kind methodology for novel transient fault correction using efficient error correcting codes with hardware scheduling for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like fault recovery time, power consumption, resource overhead and error correction efficiency to estimate the performance of our proposed methods.     

TM-CAM：一种高效的容软错误相联存储器

相联存储器是集成电路中对软错误最敏感的部件之一,但是其结构特点决定了不能使用错误保护码等传统容错方法进行保护。提出了一种容软错误的相联存储器结构TM CAM,通过采用三值匹配线机制和仔细设计的三值灵敏放大器,能够检测相联存储器中的任意一位错误,其结构简单高效。基于该结构,还提出了TM CAM的访问算法。实验表明,TM CAM能够以很小的开销有效地缓解相联存储器中的软错误问题。     

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (P_detection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average P_detection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.     

Power transition X filling based selective Huffman encoding technique for test-data compression and Scan Power Reduction for SOCs

Due to the excessive utilization of memory, data compression is an evergreen research topic. Realizing the constant demand of compression algorithms, this article presents a compression algorithm to analyse the digital VLSI circuits for constraint optimization, such as test data volume, switching power, chip area overhead and processing speed of testing. This article proposes a new power transition X filling based selective Huffman encoding technique, which achieves better data compression, switching power reduction, chip area overhead reduction and speed of testing. The performance of the proposed work is examined with the help of ISCAS benchmark circuits. Initially, the test set is occupied by using the power transition X filling technique to replace the don't care bits and the filled test set is further encoded by selective Huffman encoding technique. The experimental results show that the proposed power transition X filling based selective Huffman encoding gives effective results compared to the related data compression techniques with minimal time and memory consumption.     

面向功耗优化的CMOL电路容错映射

针对CMOS/纳米线/分子混合(CMOL)电路的缺陷导致电路功耗增加这一问题,提出基于单元限用的容错映射方法.首先建立缺陷对的功耗模型,分析常连缺陷对的映射模式对功耗的影响;然后通过高功耗单元的限用与功耗约束的设置,以减少高成本映射模式带来的功耗开销;最后采用改进的遗传算法完成电路容错映射.ISCAS标准测试电路的实验...     

适用于扫描测试中的测试响应压缩电路设计

测试向量响应压缩电路分为组合压缩电路和时序压缩电路两种．提出一种新的时序压缩电路：锥一压缩器．由于该电路是单输出的,所以总能保证最大压缩率．根据扫描测试中故障出现的特点,通过引入等价概念和两条设计规则来保证该响应压缩电路能够避免2,3和任何奇数个错误位抵消的情况．这两条设计规则同样适用于处理测试响应中出现未知位的情况．提出的基于随机选取生成算法可以自动生成该压缩电路．最后用实验数据从性能和代价两方面分析了锥一压缩器的适用性．     

A low-cost concurrent BIST scheme for increased dependability

Built-in self-test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed concurrent test latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to concurrent test latency and hardware overhead trade-off, for low values of the hardware overhead.     

一种交替互补的双状态机自恢复方案

针对深亚微米工艺下瞬态故障引发的软错误可能成为芯片失效的重要原因,提出了一种交替互补的双状态机自恢复结构,该结构将原始状态机拆分为两个子状态机,两个子状态机交替工作,互为补充.在其中一个子状态机发生错误时,回卷到另一个子状态机中的正确状态重新执行,从而有效地针对软错误引起的状态翻转进行防护.为验证本方案,对MCNC91标准电路进行了实验.实验结果显示,在面积开销略为增加的情况下,该方案防护了电路中99.64%的软错误,而电路的延迟比其他同类自恢复方案大幅度降低,在性能改进方面有一定优势.