A Multi-Agent System to Support Location-Based Group Decision Making in Mobile Teams

This paper describes an agent-based approach for developing a location-based asynchronous group decision-support system for mobile teams. The approach maximises the use of reusable service components (GSCmas — generic service component for multi-agent systems) as the main interaction mechanism between agents to allow flexible support of a new group-decision process. The paper describes the architecture of a GSCmas and provides details of how the GSCmas is integrated within a decision support system. Finally a system (mPower) based on the proposed approach is introduced and applied to a location-based group decision problem.     

I/Q multiplexed code assignment for fast cell search inasynchronous DS/CDMA cellular systems

For flexible system deployment, we consider asynchronous cell site operation which requires much longer cell search time than in synchronous operation. A new code assignment scheme is proposed to minimize the cell search time in which a group code is assigned to the in-phase pilot channel and a cell-specific code assigned to the quadrature pilot channel. Simulation results show that cell search can be accomplished in less than about 200 ms at 90% of the locations when the pilot code of length 1024 and eight group codes (64 cell-specific codes/group) are used     

A flexible multiport RAM compiler for data path

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b×2048 words and 72 b×512 words was also obtained. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1 K and 11.0 ns for 32 K     

A fault-tolerant 30 ns/375 mW 16K/spl times/1 NMOS static RAM

A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.     

An adaptive multiuser receiver for CDMA systems

A new real-time, digital adaptive multiuser receiver structure is proposed for the uplink in a mobile communications system employing code division multiple access (CDMA). The receiver efficiently implements the decorrelating detector of Lupas and Verdu (1989) and can be adapted to incorporate decision feedback to further improve the detector performance. While the basic receiver design is presented for synchronous CDMA over AWGN channels, experimental evaluation of the receiver for the asynchronous case verifies its robustness for cases when the relative user delays are small compared to the symbol duration as in microcellular scenarios. An efficient decorrelating RAKE combiner for frequency-selective multipath channels is also proposed and analyzed. Performance evaluation of the detector via computer simulation scenarios is conducted in support of analytical results to substantiate its potential for real-time operation     

Architectural optimization for low-power nonpipelined asynchronoussystems

This paper presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4     

Analysis of the metastable behaviour of a BiCMOS SR latch

The successful design of digital systems with asynchronous inputs requires careful management of timing relations. Flip-flops used as arbiters or synchronizers in these systems are under asynchronous control and thus can suffer from additional propagation delays due to metastable operation. These added delays lead to system malfunction. An analysis of metastable operation in BiCMOS SR flip-flops is presented. An analytical expression for the flip-flop resolving time is derived. Optimal sizing of the MOSFETs and BJTs is investigated analytically as well as by using SPICE simulation.     

Difference threshold test for asynchronous BFSK frequency-hoppedmultiple access systems over Rician channels

A new side information generating mechanism, the difference threshold test (DTT), is proposed to improve the capacity of asynchronous frequency-hopped multiple access systems with binary frequency shift keying (BFSK) signalling over Rician fading channels. By adjusting the threshold in the DTT decision logic, optimum capacity can be obtained. This technique has proven to be advantageous compared with the conventional hard decision technique. For systems with signal-to-noise ratio ranging from 10 to 13 dB, this improvement can be >13%     

Asynchronous control algorithms for increasing the efficiency ofthree-stage connecting networks for multipoint services

A study is made of the problem of designing low complexity control algorithms for controlling three-stage connecting networks with the objective of improving system performance. The chosen approach is based on the theory of connecting networks and makes use of rearrangement algorithms. These algorithms are applicable to a number of environments, including multipoint connections, time plan modifications in satellite systems, and real-time routing. The main feature of the algorithms is an asynchronous mode of operation for modifying the system switching configurations. A theoretical framework has been developed for defining the conditions that must hold for the asynchronous rearrangements to work. A quantitative evaluation of these algorithms obtained with a computer simulation program is given     

AMULET2e: an asynchronous embedded controller

AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks     

机载计算机RS422A通讯的软硬件设计与实现

RS422A、RS485等异步串行通讯技术广泛应用于机载计算机实时控制系统,提高了飞机的可维护性和可扩展性。为使其稳定工作,不仅需要可靠硬件平台,还需严密的软件算法。文中描述了某机载计算机为实现与多个设备进行实时异步串行通讯,设计了统一的硬件平台,并根据每个设备不同的通讯协议,给出了不同的软件算法,重点阐述了软件设计及原理。根据该原理研制的产品已经过试验、联试和用户使用,证明其工作可靠、性能良好。     

Multi-Shot Approach to Multiuser Separation and Interference Suppression in Asynchronous CDMA

In this work, we present a new, computationally simple scheme (termed multi-shot approach) to separate and detect multiuser signals in an asynchronous code-division multiple-access (CDMA) communications system. By exploring the structure inherent in the matrix decomposition of properly arranged data, obtained from multi-shot matched filtering, we propose a near-far resistant multiuser detector. The proposed multiuser detector combines the multiple snapshots of matched filter outputs through a matrix filtering and de-biasing processing, revealed from the structure inherent in properly arranged data, prior to the final stage of decision making. Simulation results demonstrate the superior performance of the newly proposed computationally efficient detection scheme in comparison with other existing methods of comparable complexity.     

交流异步电动机的软起动

由于传统交流异步电动机的起动方法有两次冲击电流,可对负载产生冲击转矩,采用晶闸管技术实现交流异步电动机软起动,介绍了该技术的工作原理。针对重载起动,传统软起动的局限性,提出采用交-交变频起动和晶闸管调压软起动相结合的方法,并通过试验测试该软起动方法能够解决重载起动时的电压波动影响,具有实际应用价值。     

An experimental 1-Mbit CMOS SRAM with configurable organization andoperation

A 1-Mb SRAM (static random-access memory) configurable as a 128-kb×8, 256-kb×4, or 1-Mb×1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7-μm geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 μm²     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

A new contactless smart card IC using an on-chip antenna and anasynchronous microcontroller

This paper describes a new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the contactless smart card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-μm technology from STMicroelectronics     

Interference Mitigation in Asynchronous Slow Frequency Hopping Bluetooth Networks

In asynchronous slow frequency hopping Bluetooth networks, packet collisions diminish the total link throughput. However, interference mitigation capability can reduce packet losses due to collisions. In this paper, an interference cancelling dual decision feedback (IC-DDF) Bluetooth receiver is proposed and its performance is evaluated for slow fading indoor channels. In addition to the bit error rate (BER) performance, the system level performance is evaluated by using the packet error rate (PER). To integrate the BER performance into the PER performance, a new geometric interpretation of packet error rate is introduced that uses an ensemble average of the received carrier to interference ratio (CIR). Also, a generalized packet collision probability is derived to analyze total link throughput.     

异步可重构结构设计

介绍一种异步可重构结构，研究了异步可重构单元的设计。通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。用三输入的C元件实现异步可重构单元的控制电路。仿真结果表明，异步可重构结构具有低功耗、高性能的优点，适合作为IP集成到系统芯片上，组成低功耗、高性能的可重构计算平台。