Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.     

Saturated spectroscopy applied to Xenon at 3.5 µm

We report the observation of the xenon isotope spectrum using saturation spectroscopy on a gain cell external to a He-Xe laser. Six resonances centered about 3.508μm are observed over the limited tuning range of the laser. These resonances are assigned to the Xe¹²⁸Xe¹³⁰Xe¹³¹Xe¹³²Xe¹³⁴and Xe¹³⁶isotopes. The observed homogeneous linewidth is 9 ± 1 MHz, and the pressure broadening of the homogeneous linewidth is experimentally determined to be 71 ± 20 MHz/ torr.     

1 µm MOSFET VLSI technology: Part VI—Electron-beam lithography

This paper discusses the fabrication of 1 µm minimum linewidth FET polysilicon-gate devices and circuits. These were designed for the tight dimensional ground rules (resolution, linewidth control, and overlay) achievable using direct wafer write scanning electron-beam lithography with individual chip registration. The present work focuses on vector-scan electron-beam technology and processing, while other papers in this series discuss other aspects of the work. Different types of 1 µm MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (on an individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.     

1 µm MOSFET VLSI technology: Part I—An overview

This paper attempts to provide a technical perspective for a 1 µm MOSFET VLSI technology described in the technical papers that follow. Highlights of various aspects of the technology development are discussed briefly. These include device design, circuit design, hot-electron effects, processing technology, electron-beam lithography, metal silicide interconnections and radiation effects.     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.     

1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage,V_{DS} = V_{GS}, is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.     

A 1-µm bipolar VLSI technology

A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I²L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I²L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I²L and STL device designs. Power-delay products of 14 fJ for I²L and 30 fJ for STL have been measured.     

Buried channel MOSFET's with gate lengths from 2.5 µm to 700 Å

High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 µm to 700 Å. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 µm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.     

1 µm MOSFET VLSI technology: Part III—Logic circuit design methodology and applications

Logic circuits were designed and fabricated in a 1 µm silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional "Weinberger" layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21- ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.     

Optical fiber tapers at 1.3 µm for self-aligned beam expansion and single-mode hardware

We have experimentally demonstrated the applicability of optical fiber tapers at 1.3 μm as a simple and practical means of achieving beam expansion in a self-aligned unitary structure. These devices have a standard 8.1-μm core at one end which gradually increases in cross section to the order of 100 μm at the other end. Tapers are envisioned as basic building blocks in a multitude of single-mode optical components. Experiments performed on a batch of eight tapers verified, to experimental accuracy, that no significant amount of mode conversion or beam distortion takes places in the taper. The insertion loss of the taper was found to be under 0.1 dB. The sensitivity of the excess loss between two tapers to lateral and axial displacement is greatly reduced as compared to that between two single-mode fibers. For example, the 0.5-dB loss point of taper coupling corresponds to a 10-μm lateral displacement and a 700-μm axial displacement versus respective 1.6-μm and 36.5-μm displacements for fiber coupling. The increased sensitivity to angular displacement is within practical limits.     

InGaAsP/InP separated multiclad layer stripe geometry laser emitting at 1.5 µm wavelength

We have developed an InGaAsP/InP separated multiclad layer (SML) stripe geometry laser emitting at 1.5 μm wavelength. In this laser, the optical confinement is done by the effective refractive index step owing to the formation of the coupled waveguide outside the stripe region. The current confinement is done by the p-n-p-n structure outside the stripe region. The CW threshold current at 25 °C is only 82 mA for the stripe width and the cavity length of 6 μm and 250 μm, respectively. The maximum temperature where the CW lasing is obtained is 65°C. The characteristic temperature of the threshold current is 60 K. The transverse mode is fundamental up to 1.8 times the threshold. Ten samples are operated at 50°C with constant optical output of 5 mW/facet. These samples are still operating at over 10 000 h with a slight increase in the driving current. The appreciable change in the characteristics due to aging is not observed.     

Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

Wavelength variation of 1.6 µm wavelength buried heterostructure GaInAsP/InP lasers due to direct modulation

Wavelength shift during the period of direct modulation (dynamic wavelength shift) for injection lasers having a BH structure has been investigated both experimentally and theoretically. A GaInAsP/InP BH laser emitting a nominal wavelength of 1.61 μm was modulated by a sinusoidal current at frequencies in the range of 0.2-2 GHz. The full width of the dynamic wavelength shift was 0.35 nm at a modulation frequency of 1.8 GHz, and a modulation depth of 63 percent at a bias current 1.14 times the threshold current. It was found that the width of the dynamic wavelength shift increases with proportion to the modulation depth, and with inverse proportion to the bias current at a frequency below 1 GHZ. The differential coefficientdn/dNof refractive indexnfor carrier densityNin the active region was measured for the purpose of the analysis. The value obtained is-1.2 times 10^{-20}cm³. The dynamic shift of the lasing wavelength was found to be characteristic of the change of the refractive index induced by the oscillation of carrier density in the active region during intensity modulation. The theoretical shift shows maximum value at a resonance-like modulation frequency. The peak height of the resonance wavelength shift is strongly affected by carrier diffusion in the transverse direction, and has a minimum value when stripe width is nearly equal to carrier diffusion length.     

Field-assisted semiconductor photoemitters for the 1—2-µm range

Photoemission data and model calculations are presented for a field-assisted semiconductor photoemitter which has achieved reflection-mode quantum efficiencies as high as 8.0 percent at 1.55 µm. The cathodes are p-p heterostructures employing lattice-matched InP-InGaAsP alloys. A thin electron semitransparent Schottky barrier provides the biasing contact for field-assisted electron emission. Parameters for optimal photoemission and sources of dark-current emission are discussed.     

New laser lines with wavelengths from λ = 61.7 µm down to λ = 27.7 µm in optically pumped CH3OH and CD3OH

25 new CW far infrared laser lines have been observed with wavelengths fromlambda = 61.7 mum down tolambda = 27.7 mum. We have significantly increased the number of known short wavelength laser lines and extended the laser line spectrum to the 30 μm region by using a BaF2outcoupling system.     

1 µm MOSFET VLSI technology: Part VII—Metal silicide interconnection technology—A future perspective

A major limitation of polycrystalline silicon as a gate material for VLSI applications is its limited conductivity which restricts its usefulness as an interconnection level. An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi2(polycide) is described. Such polycide layers are demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystalline silicon while maintaining the reliability of the polycrystalline silicon gate and the ability to form passivating oxide layers under typical polycrystalline silicon processing conditions.     

1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications

Micrometer-dimension n-channel silicon-gate MOSFET's optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fan-out and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.     

High-performance 8—14- µm Pb1-xSnxTe photodiodes

Photovoltaic detectors of Pb1-xSnxTe, sensitive in the 8- 14-µm spectral region, with near-theoretical performance characteristics, have been fabricated by a surface inversion technique. These detectors have exhibited quantum efficiencies of up to 45 percent limited by surface reflection), zero-bias resistance-area products of 21 Ωċcm²and background-limited detectivities of 1.5 × 10¹¹cm ċ Hz^1/2/W. A theoretical model consistent with experimental results is presented. Such high-performance devices are useful in guidance, reconnaissance, surveillance, ranging, and communication systems.