Two-dimensional analysis of velocity overshoot effects in ultrashort-channel Si MOSFET's

A new two-dimensional device simulator is developed to investigate the effects of velocity overshoot on Si MOSFET's. An electron temperature-dependent mobility model, in which mobility is determined as a function of electron-gas temperature, is used in the simulator. Marked velocity overshoot occurs in the vicinity of the drain edge of MOSFET's and makes the potential barrier height at the source edge lower for ultrashort-channel MOSFET's. Therefore, velocity overshoot effects appear not only as degradation of electron transit time but also as increased drain current as compared with the case in which drift velocity does not overshoot. The increase in drain current depends strongly upon low-field mobility and bias conditions and appears for channel lengths shorter than 1000 nm. When low-field mobility is higher than 500 cm²/V. s and channel length is 100 nm, the increase in drain current is more than 1.5 times for bias conditions of strong inversion and a lateral electric field of more than 10⁵V/cm in the vicinity of the drain edge.     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively     

Observation of velocity overshoot in silicon inversion layers

Employing a test structure, velocity overshoot in silicon inversion layers is observed at room temperature. For channel lengths longer than 0.3 μm, the velocity/field relation follows the well-known behavior with no channel length dependence. The first indication of velocity overshoot is seen at a channel length of 0.22 μm, while at L=0.12 μm, drift velocities up to 35% larger than the long-channel value are measured     

Influence of electron velocity overshoot on collector transit timesof HBTs

Collector transit times of heterojunction bipolar transistors with a pronounced electron velocity overshoot effect are investigated using a simple analytical model. The effective carrier velocity, ν_eff , which is a measure for determining the transit time, is defined as π_C=W_C/2ν_eff. It is found that ν_eff is much different from the average velocity, ν_av, that is given by the traveling time through the whole collector depletion layer and the depletion width. With a higher overshoot peak velocity, the collector transit time is shorter than that estimated simply from the average velocity ν_av     

Characteristics including electron velocity overshoot for0.1-μm-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n⁺-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a/L_g). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n⁺-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10⁶ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f_T of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET     

Calculation of velocity overshoot,velocity autocorrelation and hot electron noise in semiconductors from the small signal microwave mobility

The small signal behavior of semiconductors under hot electron conditions is modeled as that of a casual, linear, time-invariant system with the small signal mobility as the system transfer function. Using linear system analysis techniques the small signal velocity overshoot is calculated from the mobility thereby establishing a close link between velocity autocorrelation and overshoot. The effect on the transients due to finite collision duration, which can be important in small geometry and high speed semiconductor devices, is demonstrated. This technique allows us to calculate a number of hot electron properties without carrying out involved Monte Carlo computations. Some numerical results for silicon are given as an example.     

High field hole velocity and velocity overshoot in siliconinversion layers

We report measurements of the drift velocity of holes in silicon inversion layers. The saturation velocity of holes at 300 K is found to be strongly dependent on the effective vertical field. No hole velocity overshoot was observed down to 0.16 μm channel length at room temperature. At 77 K, hole velocity saturation is much less pronounced, and a 10% higher average velocity is observed for 0.16 μm channel length as compared to 0.36 μm channel length     

Hysteresis I-V effects in short-channel Silicon MOSFET's

Hysteresis in Ids-Vdscharacteristics is observed at high drain voltages in short-channel silicon MOSFET's biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge limited current behavior.     

Implications of velocity overshoot in heterojunction transit-time diodes

The influence of transient transport in heterojunction transittime is discussed. It is argued that overshoot effects can be important in such devices, in which case the presence of the overshoot will significantly impact device design. Appropriately designed structures are predicted to be superior to their homojunction counterparts, particularly at millimetre wavelengths.     

An investigation of steady-state velocity overshoot in silicon

Electron dynamics in silicon is investigated by means of improved momentum- and energy-balance equations including particle diffusion and heat flux. The resulting system of partial differential equations is numerically solved in a variety of field configurations including strong discontinuities, in order to enhance velocity overshoot effects. It is found that diffusion, usually neglected in previous studies, plays a major role, and considerably modifies the features of the velocity vs distance curve, leading to an increase of the carrier drift velocity in the low-field region, i.e. before experiencing the effect of the strong field. In addition, it is found that, in order to take full advantage of velocity overshoot effects in MOSFET's, a structure must be designed having the strongest possible field at the source-end of the channel, where carrier density is controlled by the gate.     

Optimization of series resistance in sub-0.2 μm SOI MOSFET's

The optimization of device series resistance in ultrathin film SOI devices is studied through 3-D simulations and process experiments. The series resistance is dependent on the contact resistivity of the silicide to silicon and the silicide geometry. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 μm, thin-film SOI devices with excellent performance and very low device series resistance     

Optimization of series resistance in sub-0.2 μm SOI MOSFET's

The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. The series resistance is dependent on the contact resistivity of the silicide to silicon and the silicide geometry. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 μm, thin-film SOI devices with excellent performance and very low device series resistance     

Microwave operation of submicrometer channel-length Silicon MOSFET's

Aluminum-gate silicon n-channel MOSFET's with channel lengths down to 0.5 µm have been fabricated. A simple four-mask process based on contact optical lithography was used. Partial self-alignment of the gate to the channel could be achieved because of an enhanced oxidation rate over the source/drain due to the heavy arsenic implantation. Accordingly, parasitics were minimized and the devices showed excellent microwave performance withf_{max}and fTnear 20 GHz.     

Verification of saturation velocity lowering in MOSFET's inversionlayer

With reduction of the MOSFET's channel length L, the drain saturation current of MOSFET's is determined by the saturation velocity v_sat in the inversion layer. Hence, the modeling of v_sat becomes very important. In this paper, v_sat in the inversion layer has been examined by using simulation experiment. New parameter values for v_sat model in the inversion layer are proposed. In order to verify the v_sat model, the impurity profiles of MOSFET's are calibrated to fit the threshold voltage V_th-L characteristics. Then, we validate new v_sat model by comparing the experiments of I_D-V_D characteristics of 0.35-μm CMOS with the simulations using the energy transport model (ETM)     

Collector signal delay in the presence of velocity overshoot

It is pointed out that the well-known expression equating the collector signal delay to one-half of the transit time through the base-collector depletion region is incorrect in the presence of a nonconstant carrier velocity, as occurs in the case of velocity overshoot. The correct expression yields a smaller signal delay than the conventional estimate for typical situations, further emphasizing the benefit of velocity overshoot in bipolar devices     

Numerical simulation of GaAs MESFETS including velocity overshoot

An effective procedure considering the velocity overshoot effect in numerical simulation of GaAs MESFETs is presented. The results of the corresponding routine SEMICO II are compared with results of Monte-Carlo simulations and with results of the routine SEMICO I without overshoot.Implanted MESFETs have been simulated with and without including the overshoot effect, and from these data equivalent circuits have been derived. From circuit calculations of E/D inverter ring oscillators it is concluded that the velocity overshoot effect leads to a twofold decrease of the gate propagation delay time for 0.25 μm gate length.     

Direct-write metallization of Silicon MOSFET's using laser photodeposition

Gate electrodes of enhancement-mode silicon MOSFET's have been written directly using a new, mask-free laser photodeposition technique. Transistor transconductances and threshold voltages were systematically tuned by varying the gate geometry with the laser beam. The new metallization process is potentially useful for tuning and optimizing the characteristics of individual devices in integrated circuits.     

Inversion channel edge in trench-isolated sub-1/4-μm MOSFET's

A comprehensive quantitative study of edge effects in the channel of trench isolated sub-1/4-μm CMOS devices is presented. Model devices derived from CMOS technologies have been examined using three-dimensional (3-D) finite element device simulation. The off-state, turn-on, and on-state device characteristics of the channel edge and terminal currents and their sensitivity to channel edge geometry, doping, oxide thickness and interface charges have been quantified. Analysis of on-state current shows that edge-effect models should include comparable contributions from decrease in threshold voltage and increase in effective width. The edge effect is shown to interact with the short-channel effect. Methods for minimizing the trench edge effect are quantified including edge doping, channel edge rounding, and recessing the channel below the top of the trench. The placement of a fixed- or floating-potential field plate in the trench is shown to be an effective method for controlling the edge effect below 100-nm channel widths     

High-field transport of inversion-layer electrons and holesincluding velocity overshoot

In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness     

Single electron switching events in nanometer-scale Si MOSFET's

High-resolution ac measurements of drain conductance at low temperatures have been made on silicon MOSFET's with channels as narrow as 0.1 µm. These devices show discrete switching events in the channel resistance associated with individual electrons being captured and emitted from single interface traps. The voltage and temperature dependence of this switching gives detailed information on the characteristics of the trap and its distance from the interface. This switching is a component of low-frequency noise in MOSFET's and may be an important limit to the performance of small transistors.