不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

Electrical and Interfacial Characterization of Atomic Layer Deposited High- κ Gate Dielectrics on GaAs for Advanced CMOS Devices

In this paper, electrical and interfacial properties of MOS capacitors with atomic layer deposited (ALD) Al₂O₃, HfO₂, and HfAlO gate dielectrics on sulfur-passivated (S-passivated) GaAs substrates were investigated. HfAlO on p-type GaAs has shown superior electrical properties over Al₂O₃ or HfO₂ on GaAs, and it is attributed to the reduction of the Ga-O formation at the interfacial layer. HfAlO on p-type GaAs exhibits the best electrical properties after postdeposition annealing (PDA) at 500degC. It is found that PDA, at above 500degC, causes a significant amount of Ga and As out-diffusion into the high-k dielectric, which degrades the interface, as well as bulk high-k properties.     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

磁控管用新型直热式稀土铪酸钆陶瓷阴极研究

为了提高大功率磁控管的输出功率,延长其使用寿命,采用难熔稀土氧化钆和过渡金属氧化铪制备大功率磁控管用新型直热式稀土铪酸钆陶瓷阴极,并对该阴极的热发射特性和寿命特性等进行了测试,热发射测试结果显示该阴极在1300℃ br即可提供0.1A/cm²发射电流密度,1600℃ br下可提供超过1.93A/cm²的发射电流密度.寿命实验结果显示,该阴极在1500℃ br,直流负载为0.5A/cm²的条件下,寿命已经超过4000h.最后,利用X射线衍射仪、扫描电镜、能谱分析仪、氩离子深度刻蚀俄歇电镜等设备分别对该阴极活性物质的分子结构,阴极表面微观形貌、元素成分及含量等进行了分析.结果表明,高温烧结合成了单一的铪酸钆物相,烧结过程中当一种Gd³⁺价稀土氧化钆掺入Hf⁴⁺价的过渡金属氧化铪时,会发生离子置换固溶,为了保持铪酸钆晶格的电中性,晶格中就会产生一个氧空位.当阴极在激活、老练、热发射测试时,会加速氧空位的生成,产生的氧空位越多,阴极表面导电性就会越好,这间接降低了逸出功,从而提高了阴极的热发射能力.     

Characterization of the Ultrathin HfO2 and Hf-Silicate Films Grown by Atomic Layer Deposition

The physical properties of HfO₂ and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 cm_-1 originate from Hf-O-Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the HfO₂/SiO ₂ interface after post deposition annealing process at 600 degC for 1 min. Moreover, the intensity of the peak at 750 cm^-1 can indicate the degree of crystallization of HfO₂. The formed Hf-silicate layer between HfO² and SiO² is also confirmed by X-ray photoelectron spectroscopy     

Structural and electrical properties of HfO2 with topnitrogen incorporated layer

A novel technique to control the nitrogen profile in HfO₂ gate dielectric was developed using a reactive sputtering method. The incorporation of nitrogen in the upper layer of HfO₂ was achieved by sputter depositing a thin Hf_xN_y layer on HfO₂, followed by reoxidation. This technique resulted in an improved output characteristics compared to the control sample. Leakage current density was significantly reduced by two orders of magnitude. The thermal stability in terms of structural and electrical properties was also enhanced, indicating that the nitrogen-doped process is effective in preventing oxygen diffusion through HfO₂. Boron penetration immunity was also improved by nitrogen-incorporation. It is concluded that the nitrogen-incorporation process is a promising technique to obtain high-k dielectric with thin equivalent oxide thickness and good interfacial quality     

High-Performance MIM Capacitors Using HfLaO-Based Dielectrics

Metal-insulator-metal (MIM) capacitors fabricated with (8%) La-doped HfO₂ single layer as well as HfLaO/ LaAlO₃/HfLaO multilayer dielectric stack are demonstrated. While the La-doped HfO₂ single layer is crystallized at 420^°C annealing, HfLaO/LaAlO₃/HfLaO multilayer dielectric stack remains amorphous. A high dielectric-constant value of 38 can be obtained when 8% La-doped HfO₂ is crystallized into cubiclike structure. However, it is observed that the linearity of MIM capacitor is degraded upon crystallization. The multilayer film has lower average dielectric constant but shows low quadratic voltage linearity of less than 1000 ppm/V² up to a capacitance density of 9 fF/?m² . It is observed that the HfLaO single-layer MIM is suitable for the applications with requirements of high capacitance density and robust reliability, while the multilayer MIM is suitable for a precision circuit.     

Atomic layer deposited HfO/sub 2/in metal?insulator?metal capacitor for RF IC applications

DC and RF characteristics of Si/SiO₂(~4 mum)/Ti/Pt-HfO₂-Al metal-insulator-metal (MIM) devices were investigated with atomic layer-deposited (ALD) high-k HfO₂ films. Excellent DC and RF properties were obtained compared to those using either SiO₂ or Si₃N₄. Both high capacitance density and small frequency-dependent capacitance reduction were observed in the MIM capacitors, in which ALD HfO₂ was used as an insulator.     

Current transport in metal/hafnium oxide/silicon structure

Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the energy band diagrams and current transport mechanisms for metal/HfO₂/Si structures. In particular, we have obtained the following quantities that will be useful for modeling and simulation: i) HfO₂/Si conduction band offset (or barrier height): 1.13 ± 0.13 eV; ii) Pt/HfO₂ barrier height: ~ 2.48 eV; iii) Al/HfO₂ barrier height: ~ 1.28 eV; iv) electron effective mass in HfO₂: 0.1 m_o, where m_o is the free electron mass and v) a trap level at 1.5 ± 0.1 eV below the HfO₂ conduction band which contributes to Frenkel-Poole conduction     

Study of the Reliability Impact of Chlorine Precursor Residues in Thin Atomic-Layer-Deposited HfO2 Layers

Atomic layer deposition (ALD) with HfCl₄ as a precursor is widely used for HfO₂ fabrication. Due to the nature of the precursor under study, i.e., HfCl₄ and H₂O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO₂ film is suspected to affect the quality of the HfO₂ film. In this paper, The authors reduced the concentration of chlorine residues by increasing the H₂O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90 s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO₂ film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO₂ layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO₂     

Low-pressure H2/N2 annealing on indium tin oxide film

Annealing of indium tin oxide (ITO) film in low-pressure H₂/N₂ was investigated. On carefully selecting the annealing process window, apparent electrical property improvement as well as good optical property can be obtained. It was found that ITO annealed with 2 Pa, H₂/N₂:6/6 sccm, at 500 °C for an hour can increase its electrical conductivity 60% more than ITO without annealing, 58% more than ITO annealed with pure H₂. An annealed ITO without specially selected recipe can easily possess worse electrical and optical properties than that without annealing. It can be explained that annealing ITO in a hydrogen-contained environment can lead to hydrogen reduction–oxygen vacancy playing a donor role in ITO; however, annealing also provides the energy to remove ITO material defects including donors.     

Fluorine Passivation in Gate Stacks of Poly-Si/TaN/HfO2 (and HfSiON/HfO2)/Si Through Gate Ion Implantation

Fluorine passivation in poly-Si/TaN/HfO₂/p-Si and poly-Si/TaN/HfSiON/HfO₂/p-Si gate stacks with varying TaN thickness through gate ion implantation has been studied. It has been found that when TaN thickness was less than 15 nm, mobility and subthreshold swing improved significantly in HfO₂ nMOSFETs; while there was little performance improvement in HfSiON/HfO₂ nMOSFETs due to the blocking of F atoms by the HfSiON layer in gate dielectrics, as has been proved by the electron energy loss spectroscopy mapping     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

The nonvolatile memory properties of the partially crystallized HfO₂ charge storage layer are investigated using short-channel devices of gate length L_g down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of L_g > 170 nm, although the reduction of the memory window is observed for devices of L_g < 170 nm. A memory window of 5.5 V, ten-year retention of V_th clearance larger than 1.5 V between adjacent levels, endurance for 10⁵ programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO₂ shows a larger memory window than HfO₂ nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO₂ matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, V_th control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si₃N₄ trapping layer.     

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Constant-voltage-bias (V_DS = V_GS = 30 V) stress measurements are performed for a period of 10⁵ s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO₂/IGZO TFTs tested exhibit the following: 1) a positive rigid log(I_D)- V_GS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I_D)-V_GS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO₂/IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I_D) -V_GS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO₂/ IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Improved Stability of High-Performance ZnO/ZnMgO Hetero-MISFETs

Improved performance and stability was demonstrated for ZnO/ZnMgO hetero-MISFETs. The MIS gate structures that were formed using either a 50-nm-thick Al₂O₃ or HfO₂ gate dielectric layer were examined by observation of the transfer characteristic hysteresis. A significantly reduced hysteresis of less than 0.1 V was obtained for HfO₂ as compared to that for the Al₂O₃ gate dielectric. By reducing the access resistance, the 1-mum gate devices showed improved transconductance values, as high as 54 mS/mm for Al₂O₃ and 71 mS/mm for HfO₂, which are the highest values ever reported for ZnO-based FETs.     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.