Kohonen神经网络在时延驱动布局中的应用

本文提出一个基于Kohonen自组织神经网络的以关键路径时延最小为优化目标的时延驱动布局算法。算法的关键是建立面向线网的样本矢量。与面向单元的样本矢量相比,面向线网的样本矢量不仅可以直接处理多端线网,而且能够描述时延信息。实验结果表明,这是一种有效的方法。     

动态可重构FPGA布局算法

SRAM(Static Random Access Memory)型FPGA凭借其动态结构调整的灵活性等特点, 被广泛应用于工业领域。针对动态可重构功能单元的布局问题, 分析了模拟退火解决方案的局限性, 提出了基于电路分层划分和时延驱动的在线布局算法。算法首先按最小分割原则将电路划分为一定数目的层, 然后按自顶向下的原则在芯片的每一层中布局划分出的层, 同时保证电路关键路径的延时最小。实验结果表明, 所述算法在时延、线长和运行时间方面均优于VPR算法。     

分级的时延驱动布局算法

本文针对门阵列和标准单元设计系统提出一种分级的时延驱动布局算法，以前的时延驱动布局算法除了文献[22]以外都不是分级的，因而运算时间很长，而且最长路径上的信号延迟达不到最优；而文献[22]的算法只能处理时序关系是DAG图（有向无环图）的电路，也就是说，电路中不能包含寄存器元件，本文的算法是适用于一般的电路．与RITUAL／Tiger系统比较，我们用比较短的运算时间得到了较小的信号延迟．     

一种时延驱动的VLSI布局方法

时廷特性对于高性能的超大规模集成电路(VLSI)来讲是十分重要的。本文提出了一个新的时延驱动的布局方法。在初始布局中,我们提出了给线网加权的新方法,在迭代改善布局中提出了等位场的概念。实验结果表明:这是一种有效的时延驱动布局方法。     

微电子学、集成电路

TN4 00()504续6用于X射线干涉纳米测量的微动工作台的有限元分析/王林,李达成,曹芒(清华大学)11光电工程.一1999,26(5).一9一12x射线干涉纳米测量系统要求分析器的俯仰角为10一8 rad量级,侧滑角为10一6 rad量级,为此设计了对称式高精度微动工作台、并利用有限元分析软件对设计的结构形式进行了分析,旨在找出影响其性能参数的主要因素,进而实现微动工作台的优化设计.图4参2(许)采用B SG(bolinded slleing grid)结构对时延驭动(tll二109 driven)或称为性能驱动(perform、needllvol)布局问题进行了研究和实现该算法是一种Nol卜slle,ng的面向…     

基于Sakurai模型的时延驱动Steiner树算法

时延驱动的Ｓｔｅｉｎｅｒ树构造算法是时延驱动总体布线的基础．本文首先简介了求解最佳Ｓｔｅｉｎｅｒ树的Ｄｒｅｙｆｕｓ－Ｗａｇｎｅｒ算法．随后通过引入Ｓａｋｕｒａｉ时延模型,提出了直接基于Ｓａｋｕｒａｉ模型的提高线网时延性能的时延驱动ＤＷ算法．当集成电路工艺的特征宽度较小时,该算法求得的Ｓｔｅｉｎｅｒ树中关键点的时延值,明显小于ＩＤＷ和ＣＦＤ算法的结果．     

面向甚大规模集成电路的时延驱动布局方法

本文针对甚大规模集成电路的时延驱动布局问题提出了一个新的解决途径,其策略是将结群技术应用于二次规划布局过程中.结群的作用是可大幅度地降低布局部件的数量.本文设计了一个高效的结群算法CARGO,其优点是具有全局最优性并且运行速度很快.采用了一个基于路径的时延驱动二次规划布局算法对结群后的电路完成布局过程.由于二次规划布局算法能够在很短时间内寻找到全局最优解,故本文的算法更有希望彻底解决甚大规模电路的布局问题.在一组MCMC标准测试电路上对算法进行了测试,得到了满意的结果.     

优化时延与拥挤度的增量式布局算法

提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%.     

VLSI总体布线算法研究与实现

总体布线是布图设计中一个极为重要的设计环节。本文提出了基于可分离最小生成树(SMST)的优化L形直角斯坦(Steiner)树(L_RST)和优化Z_RST的算法。该算法实现上绕开计算重合度问题，以新的角度计算代价。利用基于tile的结构，实现了伪管脚(pseudo pin)的分配，适用于现代多层布线需求。最后文章研究了同时考虑串扰和时延的综合性能驱动的总体布线算法改进。     

优化时延与拥挤度的增量式布局算法

提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10 % .     

一种动态密度和约束的四边布线程序

本文介绍一种新的四边通道布线器(DDCR),该布线器基于启发式原则提出,并应用动态布线密度和约束图完成线网定序和连线段选择。DDCR是H/V方式布线,该程序由C语言写成,运行于VAX11/780VMS下,可与BBL2布图系统配套使用,通过对许多例子试验,其效果是满意的。     

Mixed Conduction in an N-Type Organic Semiconductor in the Absence of Hydrophilic Side-Chains

Organic electrochemical transistors (OECTs) are the building blocks of biosensors, neuromorphic devices, and complementary circuits. One rule in the materials design for OECTs is the inclusion of a hydrophilic component in the chemical structure to enable ion transport in the film. Here, it is shown that the ladder-type, side-chain free polymer poly(benzimidazobenzophenanthroline) (BBL) performs significantly better in OECTs than the donor–acceptor type copolymer bearing hydrophilic ethylene glycol side chains (P-90). A combination of electrochemical techniques reveals that BBL exhibits a more efficient ion-to-electron coupling and higher OECT mobility than P-90. In situ atomic force microscopy scans evidence that BBL, which swells negligibly in electrolytes, undergoes a drastic and permanent change in morphology upon electrochemical doping. In contrast, P-90 substantially swells when immersed in electrolytes and shows moderate morphology changes induced by dopant ions. Ex situ grazing incidence wide-angle X-ray scattering suggests that the particular packing of BBL crystallites is minimally affected after doping, in contrast to P-90. BBL's ability to show exceptional mixed transport is due to the crystallites’ connectivity, which resists water uptake. This side chain-free route for the design of mixed conductors could bring the n-type OECT performance closer to the bar set by their p-type counterparts.     

基于BSG模型的BBL布局

布局是VLSI物理设计的关键步骤之一.对于一般的BBL布局,一个基本问题是如何对布局问题的解进行有效的表示,文献[1]提出了BSG模型并对non-slicing结构的BBL布局进行了成功的表示.文章对BSG模型进行了研究和实现,并在用模拟退火算法实现过程中进行了搜索策略的改进,得到了较好的实验结果.     

Water-gated organic nanowire transistors

We gated both p-type, and n-type, organic nanowire (NW) films with an aqueous electric double layer (EDL) in thin-film transistor (TFT) architectures. For p-type NWs, we used poly(3-hexylthiophene) (P3HT) NWs grown via two different routes. Both can be gated with water, resulting in TFTs with threshold lower than for conventionally cast P3HT films under the same gating conditions. However, TFT drain currents are lower for NWs than for conventional P3HT films, which agrees with similar observations for ‘dry’ gated TFTs. For n-type NWs, we have grown ‘nanobelts’ of poly(benzimidazobenzophenanthroline) (BBL) by a solvent/non-solvent mixing route with later displacement of the solvent, and dispersion in a non-solvent. Water-gating such films initially failed to give an observable drain current. However, BBL nanobelts can be gated with the aprotic solvent acetonitrile, giving high n-type drain currents, which are further increased by adding salt. Remarkably, after first gating BBL NW films with acetonitrile, they can then be gated by water, giving very high drain currents. This behaviour is transient on a timescale of minutes. We believe this observation is caused by a thin protective acetonitrile film remaining on the nanobelt surface.     

Laterally Ordered Bulk Heterojunction of Conjugated Polymers: Nanoskiving a Jelly Roll

This paper describes the fabrication of a nanostructured heterojunction of two conjugated polymers by a three‐step process: i) spin‐coating a multilayered film of the two polymers, ii) rolling the film into a cylinder (a “jelly roll”) and iii) sectioning the film perpendicular to the axis of the roll with an ultramicrotome (nanoskiving). The conjugated polymers are poly(benzimidazobenzophenanthroline ladder) (BBL, n‐type) and poly(2‐methoxy‐5‐(2′‐ethylhexyloxy)‐1,4‐phenylenevinylene) (MEH‐PPV, p‐type). The procedure produces sections with an interdigitated junction of the two polymers. The spacing between the phases is determined by spin‐coating (～15 nm to 100 nm) and the thickness of each section is determined by the ultramicrotome (100 to 1000 nm). The minimum width of the MEH‐PPV layers accessible with this technique (～15 nm) is close to reported exciton diffusion lengths for the polymer. When placed in a junction between two electrodes with asymmetric work functions (tin‐doped indium oxide (ITO) coated with poly(3,4‐ethylenedioxythiophene:poly(styrenesulfonate) (PEDOT:PSS), and eutectic gallium‐indium, EGaIn) the heterostructures exhibit a photovoltaic response under white light, although the efficiency of conversion of optical to electrical energy is low. Selective excitation of BBL with red light confirms that the photovoltaic effect is the result of photoinduced charge transfer between BBL and MEH‐PPV.     

混合模拟退火算法解决VLSI布局问题

VLSI布局问题是集成电路物理设计过程中的关键步骤，它直接影响整个设计的成败。Slicing结构是一种简单而高效的布局表示方法，采用正则波兰表达式编码，将模拟退火与禁忌搜索算法结合形成了一种以模拟退火算法为基础的混合算法进行求解，用MCNC benchmarks进行实验，结果表明：文章提出的混合算法比模拟退火算法在求解效率和质量上都有较大的提高。     

AN ALGORITHM OF K-LINE LOCATION FOR BBL IN LSI/VLSI

In this paper,a K-line location algorithm for building block cells in LSI/VLSI ispresented.When the relative positions of rectangular cells are given,there are 2 states accordingto the two orientations of a cell.It is proved that to find the optimum solution from the 2~N statescan be reduced to calculate the N states in K-line algorithm.So the algorithm is shown veryeffective and can be used with association for cluster method in BBL placement.Under certainconditions,this method can also be used to pesudo BBL placement directly.     

LSI/VLSI的任意元胞K行安置的算法

本文提出一种适用于LSI/VLSI任意元胞布局的K行安置的算法。当矩形单元的拓朴位置确定后,每个单元有横放、竖放两个态共有2n个态。在K行安置时,从这2n个态中选出包络矩形面积最小的问题,可归结为求n个态中的包络矩形面积最小,所以是很有效的算法。可以和结群法混合使用;在一定条件下,还可以直接用于准BBL布局。     

Highly Scalable Embedded Flash Memory With Deep Trench Isolation and Novel Buried Bitline Integration for the 90-nm Node and Beyond

In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with uniform channel program/erase by Fowler-Nordheim tunneling without gate induced drain leakage, a key feature for low-power portable electronics. The IPW concept leads to a compact cell design and a highly scalable high-voltage periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTI of each bitline (BL) from its neighboring BLs. We additionally present a buried BL (BBL) concept that links the source contacts of each individual BL via the IPW; thus, effectively eliminating one metal line per BL and reducing overall cell size. A conservative cell size shrink of about 40% can be achieved for a uniform channel program/erase-Flash cell with deep trench and BBL compared to a conventional 21F²cell.     

High Electron Mobility and Ambipolar Charge Transport in Binary Blends of Donor and Acceptor Conjugated Polymers

High electron mobility and ambipolar charge transport are observed in phase‐separated binary blends of n‐type poly(benzobisimidazobenzophenanthroline) (BBL) with p‐type polymer semiconductors, poly[(thiophene‐2,5‐diyl)‐alt‐(2,3‐diheptylquinoxaline‐5,8‐diyl)] (PTHQx) and poly(10‐hexylphenoxazine‐3,7‐diyl‐alt‐3‐hexyl‐2,5‐thiophene) (POT). Atomic force microscopy (AFM) and transmission electron microscopy (TEM) show phase‐separated domains of 50–300 nm in the binary blend thin films. The TEM images and electron diffraction of BBL/PTHQx blends show the growth of single‐crystalline phases of PTHQx within the BBL matrix. A relatively high electron mobility (1.0 × 10^–3 cm² V^–1 s^–1) that is constant over a wide blend‐composition range is observed in the PTHQx blend field‐effect transistors (FETs). Ambipolar charge transport is observed in both blend systems at a very high concentration of the p‐type semiconductor (≥90 wt % PTHQx or ≥80 wt % POT). Ambipolar charge transport is exemplified by an electron mobility of 1.4 × 10^–5 cm² V^–1 s^–1 and a hole mobility of 1.0 × 10^–4 cm² V^–1 s^–1 observed in the 98 wt % PTHQx blend FETs. These results show that ambipolar charge transport and the associated carrier mobilities in blends of conjugated polymer semiconductors have a complex dependence on the blend composition and the phase‐separated morphology.