异步可重构结构设计

介绍一种异步可重构结构，研究了异步可重构单元的设计。通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。用三输入的C元件实现异步可重构单元的控制电路。仿真结果表明，异步可重构结构具有低功耗、高性能的优点，适合作为IP集成到系统芯片上，组成低功耗、高性能的可重构计算平台。     

PVHArray:一种流水可伸缩的层次化可重构密码逻辑阵列结构

针对密码算法的高效能实现问题,该文提出了一种基于数据流的粗粒度可重构密码逻辑阵列结构PVHArray.通过研究密码算法运算及控制结构特征,基于可重构阵列结构设计方法,提出了以流水可伸缩的粗粒度可重构运算单元、层次化互连网络和面向周期级的分布式控制网络为主体的粗粒度可重构密码逻辑阵列结构及其参数化模型.为了提升可重构密码逻辑阵列的算法实现效能,该文结合密码算法映射结果,确定模型参数,构建了规模为4×4的高效能PVHArray结构.基于55nm CMOS工艺进行流片验证,芯片面积为12.25mm²,同时,针对该阵列芯片进行密码算法映射.实验结果表明,该文提出高效能PVHArray结构能够有效支持分组、序列以及杂凑密码算法的映射,在密文分组链接（CBC）模式下,相较于可重构密码逻辑阵列REMUS_LPP结构,其单位面积性能提升了约12.9%,单位功耗性能提升了约13.9%.     

一种数据流处理器的异步流水结构设计

介绍了一种基于握手协议的异步数据流处理器.首先阐述了数据流处理器的基本结构,4相捆绑数据握手协议.并随后根据DFP自身特点提出了改进式自控式单元结构应用于握手协议的硬件实现,以及2级循环分支流水结构应用于异步流水.最后就基本操作运算对该结构进行了仿真验证.     

面向VLSI实现的实时自适应滤波算法

本文提出了一种面向ＶＬＳＩ实现的复数域递推最小二乘算法，算法中所有的运算都映射到一个全由ＣＯＲＤＩＣ单元组成的脉动阵列并行处理结构中。该阵列可直接对数据矩阵进行线性约束的自适应滤波而避免了复杂的滤波器复权系数求解。本文还介绍了为该算法设计的超大规模专用集成电路芯片，利用该芯片可组成数据采样率为２ＭＨｚ的可重构的实时自适应滤波器。     

一种基于流处理框架的可重构分簇式分组密码处理结构模型

可重构密码处理结构是一种面向信息安全处理的新型体系结构,但具有吞吐量和利用率不足的问题。该文提出一种基于流处理框架的阵列结构可重构分组密码处理模型(Stream based Reconfigurable Clustered block Cipher Processing Array, S-RCCPA)。针对分组密码算法特点,采用粗粒度可重构功能单元、基于Crossbar的分级互连网络、分布式密钥池存储结构以及静态与动态相结合的重构方式,支持密码处理路径的动态重组,以不同并行度的虚拟流水线执行密码任务。对典型分组密码算法的适配结果表明,在 CMOS工艺下,依据所适配算法结构的不同,规模为41的S-RCCPA模型的典型分组密码处理性能可达其它架构的5.28~47.84倍。     

片上网络GALS接口设计

本文提出了一种基于握手协议的GALS接口设计方法。该接口采用异步FIFO作为输入缓冲区,有效降低了数据传输延迟;采用环形缓冲的概念来管理缓冲区,使接口具有了可扩展性。FPGA验证结果表明,该接口保证了适配单元与网络路由之间完成准确的异步传输,4通道的接口共占用了405个ALUT（Adaptive Look-Up Table）和支持211 MHz的时钟频率。     

一种面向序列密码的混合粒度并行运算单元

针对可重构密码处理器对于不同域上的序列密码算法兼容性差、实现性能低的问题,该文分析了序列密码算法的多级并行性并提出了一种反馈移位寄存器(FSR)的预抽取更新模型。进而基于该模型设计了面向密码阵列架构的可重构反馈移位寄存器运算单元(RFAU),兼容不同有限域上序列密码算法的同时,采取并行抽取和流水处理策略开发了序列密码算法的反馈移位寄存器级并行性,从而有效提升了粗粒度可重构阵列(CGRA)平台上序列密码算法的处理性能。实验结果表明与其他可重构处理器相比,对于有限域(GF)(2)上的序列密码算法,RFAU带来的性能提升为23%～186%;对于GF(2u)域上的序列密码算法,性能提升达约66%～79%,且面积效率提升约64%～91%。     

一种新结构FFT算法及其FPGA实现

本文给出了一种面向FPGA实现的新结构FFT算法,并利用FPGA器件内部丰富的逻辑单元,RAM、ROM和DSP块实现了FFT核心运算的并行化,与利用传统结构实现的FFT相比大大提高了FFT的运算速度,与用DSP实现的FFT相比速度也要快得多。     

基于FPGA的快速傅里叶变换FFT处理器设计

FFT是DFT的快速算法,广泛应用于语音处理、数字通信、计算机等领域。该设计基于FPGA实现,采用基2时域抽取FFT算法,以倒序输入,顺序输出的方法实现字长为12位的256点FFT变换,将蝶形运算单元设计成为一种只需3个时钟周期就能进行一次蝶形运算的特殊结构,使蝶形运算的时间大大缩减。在系统仿真时以两个正弦波的叠加信号为测试信号,在Modelsim中进行仿真,验证设计的正确性。     

一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现

硬件木马检测已成为当前芯片安全领域的研究热点,现有检测算法大多面向ASIC电路和FPGA电路,且依赖于未感染硬件木马的黄金芯片,难以适应于由大规模可重构单元组成的粗粒度可重构阵列电路。因此,该文针对粗粒度可重构密码阵列的结构特点,提出基于分区和多变体逻辑指纹的硬件木马检测算法。该算法将电路划分为多个区域,采用逻辑指纹特征作为区域的标识符,通过在时空两个维度上比较分区的多变体逻辑指纹,实现了无黄金芯片的硬件木马检测和诊断。实验结果表明,所提检测算法对硬件木马检测有较高的检测成功率和较低的误判率。     

Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5times smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.     

基于SOPC可重构的图像采集与处理系统设计

针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。     

FPGA Implementation and Energy Cost Analysis of Two Light-Weight Involutional Block Ciphers Targeted to Wireless Sensor Networks

In this paper, we investigate the energy cost of the FPGA implementation of two cryptographic algorithms targeted to wireless sensor networks (WSNs). Recent trends have seen the emergence of WSNs using sensor nodes based on reconfigurable hardware, such as a field-programmable gate arrays (FPGAs), thereby providing flexible functionality with higher performance than classical microcontroller based sensor nodes. In our study, we investigate the hardware implementation of involutional block ciphers since the characteristics of involution enables performing encryption and decryption using the same circuit. This characteristic is particularly appropriate for a wireless sensor node which requires the function of both encryption and decryption. Further, in order to consider the suitability of a cipher for application to a wireless sensor node, which is an energy constrained device, it is most critical to consider the cost of encryption in terms of energy consumption. Hence, we choose two involutional block ciphers, KHAZAD and BSPN, and analyze their energy efficiency for FPGA implementation.     

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-2²/2³/2⁴ FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.     

基于AES加密电路的防复制电路及系统设计

随着各种抄板技术和芯片解剖技术的发展,嵌入式系统芯片正面临着越来越多受攻击风险,如何保护嵌入式系统产品不受非法复制,正日益受到人们的关注,各种防复制方法也应运而生。由此设计了一款软硬件协同的新型防复制电路及系统,用以实现对嵌入式软件版权的保护。防复制电路采用AES加密算法与嵌入式芯片进行多次随机动态加密验证,使破解者无法通过监控通信数据来破解验证保护。防复制电路中内置CPU和安全存储器,用来存储关键数据以及执行部分嵌入式程序,让破解者无法获得嵌入式芯片中完整的程序,从软硬件两方面实现了对嵌入式产品版权的充分保护。本电路在FPGA上进行了实现,并搭建被保护芯片与防复制FPGA电路的联合保护系统,实测结果显示该系统很好的完成了防复制的功能,未通过动态加密验证无法启动系统,此外,没有防复制电路的配合,无法执行完整的嵌入式芯片中的程序。     

Encrypted Biography of Biomedical Image - a Pentalayer Cryptosystem on FPGA

Secure transmission of medical information occupies a crucial role in the world of telemedicine applications. Reconfigurable hardware implementation offers several advantages over software implementation especially for real time security applications. This work aims to propose the novel implementation of a penta-layer medical image encryption using a reconfigurable Cyclone II Field Programmable Gate Array (FPGA) EP2C35F672C6. The first layer of encryption performs the row-wise and column-wise pixel permutations based on Linear Feedback Shift Register (LFSR). The second and third layers of encryption are based on maximal length sequence Pseudo Random Number Generator (PRNG) 16-bit Cellular automata (CA) circuit and Galois Field (GF) product. In the fourth layer, a synthetic image is subsequently created by chaotic clock with Phase Lock Loop (PLLs) and gates to diffuse the image pixels. This creation of synthetic image for diffusion makes the developed cryptosystem totally hardware dependent. Last layer performs the diffusion using one dimensional logistic map. The synthesized result reveals that the reconfigurable implementation of proposed encryption process consumes comparatively lesser logic elements (2480) and low power consumption (278.65 mW) with an encryption time of 215.92 ms for encrypting a 256?×?256 DICOM medical image. Finally, various analyses such as Number of Pixel Change Rate (NPCR), Unified Average Change in Intensity (UACI), Entropy, Correlation, Uniform distribution and NIST statistical test suite have been performed to prove the robustness of the algorithm against various attacks.

     

FPGA Implementation(s) of a Scalable Encryption Algorithm

SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this letter, we investigate its performances in field-programmable gate array (FPGA) devices. For this purpose, a loop architecture of the block cipher is presented. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. The letter also carefully describes the implementation details allowing us to keep small area requirements. Finally, a comparative performance discussion of SEA with the advanced encryption standard Rijndael and (a cipher purposed for efficient FPGA implementations) is proposed. It illustrates the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency.     

一种专用可重配置的FPGA嵌入式存储器模块的设计和实现

本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write_first、no_change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想.