Culturally embedded computing

In culturally embedded computing, we begin by examining how the technology is emblematic of its cultural context. Culturally embedded computing explicitly situates embedded computing in society, individual experience, culture, and history. Based on this new emphasis, five projects explore alternatives to traditional human-computer interaction design. Designing and building these new technologies requires more than simply building and understanding hardware and software. It also requires analyzing and incorporating the stories, meanings, and social networks that these devices engage.     

Configurable processors for embedded computing

We have all heard about the increasing software content of embedded systems. To those who think of embedded software as autonomous programs hidden deep within the system, plugging away transparently and reliably on dedicated tasks, this increase might suggest that these programs are somehow becoming larger. In reality, the ongoing increases in processor performance let system designers implement in software what previously required dedicated or custom hardware blocks and accelerators. Indeed, given a choice, system designers might actually prefer the flexibility of implementing all embedded applications in software on programmable processors. However, parts of the applications must often run under critical time, performance, power, and cost constraints. Thus, designers have traditionally mapped these segments into custom hardware, such as application-specific integrated circuits (ASICs), or into reprogrammable fabrics, such as field programmable gate arrays (FPGAs). Ever-increasing chip capacities have given rise to configurable processors that offer virtually unlimited choices in core architectures.     

What is embedded computing?

An embedded system is any computer that is a component in a larger system and that relies on its own microprocessor. Evolving from a craft to an engineering discipline over the past decade, embedded computing continues to mature. The purpose of this article is to demonstrate that embedded computing is an established engineering discipline with principles and knowledge at its core     

Membrane computing and brain modelling

We briefly discuss variants of (extended) spiking neural P systems that combine features from the areas of membrane computing and spiking neurons. This work was presented in part at the 13th International Symposium on Artificial Life and Robotics, Oita, Japan, January 31–February 2, 2008     

Continuity aspects of embedded reconfigurable computing

In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.     

Trustworthy ICs for secure embedded computing

The design of secure and trusted embedded systems has recently drawn enormous attention from system-design practitioners. A secure system is only as strong as the weakest link. Therefore, any security functions implemented in an embedded system must be considered in both hardware and software, at all design abstraction levels, in communications between components, and in the manufacturing phase. In addition, these implementations are subject to typical power, performance, and cost constraints of consumer embedded systems. This issue of IEEE Design & Test features a special issue on Design and Test of Integrated Circuits for Secure Embedded Computing.     

异构多处理器嵌入式计算平台的设计

提出了采用异构多处理器体系结构构建嵌入式计算平台的思想,并基于该思想采用Cortex M3主处理器和MSP430协处理器构建了异构多处理器体系结构的433 MHz有源RFID读写机具。实际验证结果表明,采用异构多处理器构建的嵌入式计算平台实现了计算密集型应用与控制密集型应用的有效分离,大大提高了系统的灵活性和资源分配的合理性。基于该体系结构重构传统嵌入式计算平台时对应用系统透明,使其具有广泛的应用前景。     

Whither Warhol's law? [embedded computing]

The article discusses a law concocted by the author: "Warhol's Law of Computer Systems Architecture." This law stated that every computer architecture would be the price-performance leader for 15 minutes. The author was thinking mainly of workstation CPUs, but he believed the embedded CPU market would follow suit. Embedded systems provide an ideal forum for CPU competition. A lot of people seemed to want to design CPUs, so the author reasoned that no end of new competitors would appear to introduce new features and drive down prices. It hasn't worked out that way, however. The high-end market has several players, but not the profusion expected a few years go.     

A multilevel computing architecture for embedded multimedia applications

We have designed a new architecture that simplifies integration of heterogeneous IP for multimedia and streaming applications. The multilevel computing architecture (MLCA) is a template architecture featuring multiple processing units. This template architecture for SOC systems uses superscalar techniques to exploit task-level parallelism among different processing units. It supports a natural programming model that relieves programmers from explicitly synchronizing tasks and communicating data. code transformations that improve application performance are easy to incorporate in compilers for this architecture.     

基于嵌入式计算平台的智能电池系统的设计

针对基于嵌入式计算平台的便携式电子设备,为其设计了一种可通用的智能电池系统(smart battery system,SBS),并详细地介绍了该系统的组成结构、基本原理、硬件构成及软件设计。由于在某些情况下嵌入式主机与智能电池直接采用SMBUS总线通信实现困难且不易移植,故利用单片机作为二者之间的通信桥梁,将智能电池作为嵌入式主机的串口设备进行处理。应用结果表明,整个智能电池系统试验运行良好,安全性好,可靠性高,成本低,可移植性佳。     

Efficient sorting design on a novel embedded parallel computing architecture with unique memory access

Embedded Parallel computing architecture with Unique Memory Access (ePUMA) is a domain-specific embedded heterogeneous 9-core chip multiprocessor, which has a unique design with low power and high silicon efficiency for high-throughput DSP in emerging telecommunication and multimedia applications. Sorting is one of the most widely studied algorithms, more embedded applications also need efficient sorting. This paper proposes an efficient bitonic sorting algorithm eSORT for the novel ePUMA DSP. eSORT algorithm consists of two parts: an in-core sorting algorithm and an intra-core sorting algorithm. Both algorithms are adapted to the novel architecture and take advantage of the ePUMA platform. This paper implemented and evaluated the eSORT for variable datasets on ePUMA multi-core DSP and compared its performance with the Cell BE processors with the same SIMD parallelization structure. Results show that bitonic sort on ePUMA multi-core DSP has much better performance and scalability. Compared with optimized bitonic sort on Cell BE, the in-core sort is 11 times faster and intra-core sort is 15 times faster in average.     

Membrane computing and complexity theory: A characterization of PSPACE

A P system is a natural computing model inspired by information processing in cells and cellular membranes. We show that confluent P systems with active membranes solve in polynomial time exactly the class of problems PSPACE. Consequently, these P systems prove to be equivalent (up to a polynomial time reduction) to the alternating Turing machine or the PRAM computer. Similar results were achieved also with other models of natural computation, such as DNA computing or genetic algorithms. Our result, together with the previous observations, suggests that the class PSPACE provides a tight upper bound on the computational potential of biological information processing models.