A new MOSFET with large-tilt-angle implanted drain (LATID)structure

The LATID device features the elimination of the sidewall spacer and self-alignment of n^- large tilt angle (LAT) and n⁺ implants to the same gate edge. Even without a spacer and a heavy drive-in, the LATID can achieve both a sufficiently long L_n- and an n⁺ gate overlap. The LATID achieves improved current drive by more than 50% and improved hot-carrier lifetime by more than three orders of magnitude as compared with a conventional lightly doped drain. The LATID technique is most promising for applications to submicrometer ULSI under 5-V operation     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as Vthlowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.     

Improved analog hot-carrier immunity for CMOS mixed-signalapplications with LATID technology

This paper reports the results of an investigation of hot-carrier effects on analog performance in LATID (Large-Angle-Tilt-Implanted-Drain) and conventional LDD submicron CMOS technology. The investigation focuses on hot-carrier induced degradation of voltage gain, degradation of drain output resistance, and drift of offset voltage of differential pairs. Results illustrate that LATID technology significantly out-performs LDD technology in regard to hot-carrier immunity of key analog parameters in short channel length devices as well as in relatively long channel length devices. The improvement of analog hot-carrier immunity with LATID is attributed to the mechanisms of reduction and departure of high electrical field from the drain area. Results suggest that LATID technology is a promising candidate for mixed-signal ULSI applications     

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-MbDRAM's

A 0.3-μm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design     

Arsenic and phosphorus double ion implanted source/drain junctionfor 0.25and sub-0.25-μm MOSFET technology

An arsenic and phosphorus double implanted source/drain junction is proposed for 0.25- and sub-0.25-μm NMOSFET technology. Arsenic is for the shallow high concentration region beneath the silicide, and phosphorus is for the slightly deeper junction to increase junction quality and to reduce junction capacitance. The arsenic and phosphorus double implantation is performed after sidewall formation. The double implanted source/drain junction shows a drastic reduction of reverse leakage current and little effect on the short channel characteristics compared with an arsenic only implanted device. Moreover, the circuit performance is improved by about 2.5%     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

Double ion implanted V-MOS technology

An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 /spl mu/m) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-/spl Aring/ gate oxide thickness.     

Ion implanted integrated optics (I3O) technology for planar lightwave circuits fabrication

The Ion Implanted Integrated Optics (I3O) technology, using titanium ion implantation in bulk silica to fabricate passive compact planar lightwave circuits (PLCs), is presented in this paper. Its advantages are described and compared with other waveguide fabrication technologies. It is demonstrated that the guided electromagnetic field can be tailored by adjusting the titanium ion dose either to fit the guided mode of standard single-mode fibers or to allow a sharp radius of curvature of bent waveguides.     

Schottky barrier thin-film transistor (SBTFT) with silicidedsource/drain and field-induced drain extension

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10⁶ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications     

A simplified fully implanted bipolar VLSI technology

An implanted n-p-n bipolar transistor structure named Isoplanar Z II (currently, being marketed as FAST-Z technology) with reduced process and masking steps is described. The simplification is achieved by employing self-aligned-transistor (SAT) masking, ion-implantation techniques to provide impurity doping, and using one common annealing cycle for collector, base, and emitter implantations. The device structure reduces design constraints through use of self-aligned field implantation and SAT mask for contact window definition. Submicrometer emitter widths are obtained by step and repeat optical photolithographic tool and two-dimensional effect on current gain due to sidewall injection is also studied. This technology is used to demonstrate 13-15 ns TAA, 4K static RAM and minimum delay of 250 ps per gate, gate array products.     

An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices

MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 μ m LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n^? drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of I–V data. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual $\text{T}{}^{\mathrm{<mtext>3</mtext><mtext>2</mtext>}}$ manner.     

High-performance implanted base silicon bipolar technology for RFapplications

A 0.4 μm silicon bipolar technology for mixed digital/analog RF-applications is described. Without increasing the process complexity in comparison to current production technologies transit frequencies of 52 GHz, maximum oscillation frequencies of 65 GHz and minimum noise figures of 0.7 and 1.3 dB at 3 and 6 GHz are achieved. Emitter-coupled logic (ECL) ring oscillators have a minimum gate delay of 12 ps, the low power capability of the technology is proven by a current-mode logic (CML) power delay product of 5.2 fJ and a dynamic frequency divider operates up to 52 GHz. These results demonstrate the suitability of this technology for mobile communications up to at least 6 GHz and for high-speed optical data links at 10 Gbit/s and above     

Increased drain saturation current in ultra-thinsilicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4×10¹⁶ cm^-3, the drain saturation current in ultrathin SOI transistors is predicted to be ~40% larger than that of bulk structures. An increase of ~30% is seen in measurements made on devices in 1000-A SOI films     

A polysilicon source and drain MOS transistor (PSD MOST)

An MOS transistor is described in which the source and drain areas are obtained by diffusion from doped polycrystalline silicon. Polysilicon tracks form the interconnect with the diffusion areas without the need for contact windows. As a result transistor and junction sizes are reduced by a factor 2 or 3 over a normal structure. Polycrystalline silicon tracks in this new technique are of greater advantage as interconnect layers than in the silicon gate tecgnique.     

Source to drain resistance beyond pinch-off in metal-oxide-semiconductor transistors (MOST)

A detailed analysis is performed yielding source to drain resistance of MOS transistors in the saturation region. The analysis is based on a depletion model of the pinched-off region of the channel. Good agreement is found between theory and experimental results obtained onN-channel silicon MOS transistors (channel length ∼5 µ).     

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm