Level-specific lithography optimization for 1-Gb DRAM

A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography     

256-Mb DRAM circuit technologies for file applications

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25-μm phase-shift optical lithography, and its basic operations are verified. A 0.72-μm² double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 μA and an access time of 48 ns     

A four-level storage 4-Gb DRAM

A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-μm CMOS technology measures 986 mm². The memory cell is 0.23 μm². Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST     

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM

An on-wafer built-in self-test (BIST) technique has been developed to implement a 200 Gb/s failed-bit search for a 1-Gb DRAM. The BIST circuits include a 4-kb very-long word bus and an on-wafer test management unit to probe DRAM arrays and compress test results. The 1-Gb DRAM is fabricated as a test device using a 0.16-μm CMOS technology. As a result, the BIST reduces the wafer test time to less than 1/100 that of bit-by-bit testing     

An experimental 220-MHz 1-Gb DRAM with a distributed-column-controlarchitecture

A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing margin between the activation of column selection lines, reducing the cycle time by 25%. To evaluate this architecture, an experimental synchronously operating 1-Gb DRAM was designed and fabricated using a 0.16-μm CMOS process. It operates with a 22O-MHz clock and a 1.5-V power supply     

A 1.5-V DRAM for battery-based applications

Circuit techniques for 1.5-V CMOS DRAMS to be used in battery-based applications are presented. A three-level word pulse and a plate pulse are used to maintain the stored voltage in a memory cell, in spite of the minimized data-line voltage swing for reducing power dissipation. A 3.4- mu m/sup 2/ data-line shielded stacked capacitor (STC) cell is also proposed to enhance signal-to-noise ratio (SNR) in the memory cell array. The 1.5-V read/write operation is observed successfully through a 2-kbit test device. The data-holding time and alpha -particle-induced soft error rate of the device indicate that the possible performances for the 1.5-V DRAM are comparable to those for the existing 5-V DRAMs.<>     

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.     

A low-jitter mixed-mode DLL for high-speed DRAM applications

This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-μm triple-metal CMOS process and occupies a die area of 0.45 mm². Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply     

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchicalsquare-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm² cell and 581.8 mm² small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described     

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

A fast 256K DRAM designed for a wide range of applications

A 256K DRAM designed for a variety of organizations and operation modes is described. The chip may be organized as 64K/spl times/4, 128K/spl times/2, or 256K/spl times/1. Four data I/O buffers are selectable by gate signals. Besides the standard RAM mode, it may be operated in the page mode, in the parallel or serial buffer mode, and in a combination of page and serial buffer modes. With these options, the design covers a wide range of applications. RAS/CAS access times are 80.55 ns. In the combined page and serial buffer mode, a data rate of up to 50 MHz is possible. The chip is built in metal-gate n-channel technology with 2-/spl mu/m minimum line width and two metal interconnection planes.     

应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器

A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.     

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells     

Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

In this letter, we present a novel junction integration scheme that enables vertical transistors to have high performance, low leakage, and easy scalability. Controlled solid-phase diffusion is used to form the vertically self-aligned buried strap junction of the vertical transistor. The electric field at the capacitor node junction is carefully optimized by creating a graded junction profile, resulted from a combination of out-diffusion from Arsenic-doped poly-silicon and Phosphorus-doped oxide. The Phosphorus-doped oxide serves as the dopant source for the vertical lightly doped drain, as well as the spacer for the high dose junctions. Integration of the self-aligned junctions into a vertical transistor dynamic random access memory (DRAM) process flow is presented. Significant improvement in the retention characteristics of a 256-Mb DRAM product confirms the applicability of this newly developed junction integration scheme for future DRAM generations.     

A CMOS burst-mode optical transmitter for 1.25-Gb/s ethernet PON applications

This brief presents a CMOS burst-mode optical transmitter suitable for use in 1.25-Gb/s Ethernet passive optical network applications. Based on feedback from the monitoring photodiode, in order to control consecutive burst data the proposed transmitter in this brief uses a reset mechanism, which allows fast responses from the beginning of a high-speed input burst. The chip is fabricated in mixed-mode 0.18-/spl mu/m CMOS technology and measurements are implemented in a chip-on-board configuration using a pig-tailed type Fabry-Perot laser. Under burst-mode operation of 1.25-Gb/s pseudorandom binary sequences, measurements show about 1-dBm averaged transmitted optical power with an over 12-dB extinction ratio over a wide temperature range.     

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm², in spite of a 1.3-μm lithography level     

Fabrication and performance of selective HSG storage cells for 256Mb and 1 Gb DRAM applications

Fabrication of rapid thermal nitrided HSG transformed crown capacitor storage cells incorporating an ultrathin low pressure chemical vapor deposition (LPCVD) Ta₂O₅ and Si₃N ₄/SiO₂(NO) dielectric is proposed. 256 Mb array with HSG crown cells of 0.3 μm diameter×0.6 μm height and 49 A T_eff showed an area enhancement factor of 1.7 (relative to untransformed crown cell). C_min/C_max ratio of >0.95, and capacitance of 16.7 fF/cell is obtained. A measured leakage current density of 0.7 nA/cm² at 1.2 V is reported. Metal-oxide-semiconductor capacitor (MOSCAP) devices with HSG electrodes for 1 Gb application are characterized using capacitance-voltage (C-V) and current-voltage (I-V) analyses. Detailed HSG grain characterization results are presented with correlation to the electrical behavior of the devices. Devices are formed using LPCVD Ta₂O₅ and/or Si₃N₄ dielectric. HSG films formed from 4×10²⁰ atoms/cc phosphorus doped amorphous silicon show depletion in C-V behavior. It is shown that phosphine doping of HSG film is required to avoid depletion. Process selectivity of the UHV/CVD HSG transformation mechanism applied to thermal oxide and nitride field dielectrics is fully explored. Selectivity limits for different types of dielectric are also presented. Effect of critical parameters such as a-Si dopant concentration, HSG incubation time, anneal conditions, and a-Si layer thickness on HSG transformation are discussed for 1 Gb crown cells     

High-speed charge transfer sense amplifier for 0.5 V DRAM array applications

A new high-speed charge transfer sense amplifier scheme is proposed for 0.5 V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts.     

A 1-Mbit BiCMOS DRAM using temperature-compensation circuittechniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V_cc variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs     

A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 10/sup 11/ cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.