Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a DC-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-N prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the sensitivity. Variable-gain amplifiers with DC-offset cancellation loop eliminate the DC-offset in each stage. The chip implemented in 0.35-/spl mu/m CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows -115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption.     

A 2-GHz wide-band direct conversion receiver for WCDMA applications

A 2-GHz direct conversion receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-μm BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-μm CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The receiver draws 128 mA from a 2.7-V supply     

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The receiver has been fabricated with a 0.35-μm 45-GHz f_T SiGe BiCMOS process     

IQ imbalance compensation scheme in the presence of frequency offset and dynamic DC offset for a direct conversion receiver

A direct conversion architecture reduces the cost and power consumption of a receiver. However, a direct conversion receiver may suffer from direct current (DC) offset, frequency offset, and IQ imbalance. This paper presents an IQ imbalance estimation scheme for orthogonal frequency division multiplexing (OFDM) direct conversion receivers. The proposed IQ imbalance estimation scheme operates in the presence of dynamic DC offset and frequency offset. The proposed scheme calculates IQ imbalance from a simple equation. It employs the knowledge of the preamble symbols of the IEEE 802.11 a/g standards, while it does not require the impulse response of the channel. Numerical results obtained through computer simulation show that the bit error rate (BER) performance for the proposed IQ imbalance estimation scheme has a degradation of about 4dB with a large DC offset, frequency offset, and IQ imbalance.     

A direct conversion receiver for satellite communication systems

A direct receiver is an alternative to the well‐established super‐heterodyne receiver. It is especially attractive to highly integrated low‐cost terminals since it eliminates the need for components at intermediate frequencies. There is increasingly more interest in using it in various ground/space‐based systems. This article presents a new direct quadrature receiver that uses three channels with different phase shifts and a novel technique to derive the in‐phase and quadrature baseband signals independent of the actual gains and phases in the receiver chains. The new technique relies on the property that the in‐phase and quadrature signals are orthogonal, and its implementation involves the signal subspace decomposition and projection. Computer simulations and a 90 Mbps Ka‐band prototype receiver have demonstrated that the performance of the receiver closely matches the theory. Copyright © 2005 John Wiley & Sons, Ltd.     

Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

A high sensitivity and wide dynamic range zero-IF RF receiver for cognitive radio application

This paper presents an RF receiver of zero-Intermediate Frequency (IF) architecture for Cognitive Radio (CR) communication systems. Zero-IF architecture reduce the image reject filter and IF filter, so it is excellent in low cost, compact volume, and low power dissipation. The receiver employs three digital attenuator and a high gain, high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of −81 dBm. A fully balanced I/Q demodulator and a differential Local Oscillator (LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage. In order to select an 8 MHz-channel from 14 continuous ones located in UHF band (694–806 MHz) accurately, approach of channel selectivity circuits is proposed. The RF receiver has been designed, fabricated, and test. The measured result shows that the noise figure is 3.4 dB, and the error vector magnitude is 7.5% when the input power is −81 dBm.     

Imbalance-compensated direct down conversion receiver for UMTS base stations

In this work, a new method for the estimation and the compensation of in-phase quadrature-imbalances in direct down conversion receivers is presented. The considerations are based on a receiver structure that is developed for the simultaneous down conversion of up to four neighboring carriers in universal mobile telecommunications system base stations. The image suppression of the system must achieve at least 60 dB. This requirement is not fulfilled by the analogue part and hence, an error estimation and compensation in the digital domain is necessary. In laboratory measurements using a wideband code-division multiple-access signal, the image suppression of the complete set-up including the analogue parts could be improved by 34 dB.     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/√Hz (rms), resulting in a very low detectable input current of 1 μ A with SNR=5.     

97dB动态范围、带温度补偿的MEMS电容传感器读出电路

This paper presents a charge-sensitive-amplifier(CSA)based readout circuit for capacitive microelectro-mechanical-system(MEMS)sensors.A continuous-time(CT)readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits.An operational trans-conductance amplifier(OTA)structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal.An analog temperature compensation method is proposed,which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity.The chip is designed and implemented in a 0.35 m CMOS process and is 2.1 2.1 mm2in area.The measurement shows that the readout circuitachieves0.9aF/√Hz capacitive resolution,97dBd ynamic range in 100Hz signal bandwidth,and 0.8mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.     

RF front-end of direct conversion receiver RFIC for cdma-2000

We report on the front-end of a highly integrated dual-band direct-conversion receiver IC for cdma-2000 mobile handset applications. The RF front-end included a CELL-band low-noise amplifier (LNA), dual-band direct-conversion quadrature I/Q down-converters, and a local-oscillator (LO) signal generation circuit. At 2.7 V, the LNA had a noise figure of 1.2 dB and input third-order intermodulation product (IIP3) of 9 dBm. I/Q down-converters had a noise figure of 4-5 dB and IIP3 of 4-5 dBm and IIP2 of 55 dBm. An on-chip phase-locked loop and external voltage-controlled oscillator generated the LO signal. The receiver RFIC was implemented in a 0.35-/spl mu/m SiGe BiCMOS process and meets or exceeds all cdma-2000 requirements when tested individually or on a handset.     

面向多用户的高动态范围视频动态范围可分级编码

提出了面向多用户的高动态范围(HDR,high dynamic range) 视频动态范围可分级编码方法,并利用视觉掩蔽特性抑制了噪声,提高了动态范围可 分级编码的效率。首先,考虑HDR视频感知特性,提出了动态范围可分级模型(DRSM,dynamic range scalable model),将不同动态范围级的HDR视频分解成为一个标准动态范围(SDR,s tandard dynamic range) 视频和多个残差信号帧(RSFs,residual signal frames)序列。然后,结合亮度掩蔽效应和 人眼感知特性,对 RSFs进行量化和滤波处理,滤除残差中的零散数据点,保留RSFs相邻动态范围级之间的整体 差异信息, 提高RSFs的编码效率。最后,在解码端重建得到SDR视频和各个动态范围级的HDR视频,以适 应多用 户端MDR显示设备。结果表明,所提出方法能在保持重建HDR视频的主观感知质量的同时降低 编码码率, 并在全帧内预测编码模式下,相同HDR-VDP-2.2和PSNR分值时,BD-rate (Bjntegaard D elta rate)平均节省了32.03%和31.28%,其编 码率失真性能有明显提升。     

一种应用于LTE直接变频无声表滤波器接收机的1.2-V CMOS前端设计

本文提出了一种应用于LTE直接变频接收机的CMOS射频前端电路。电路由低噪声跨导放大器（LNA）,电流型无源混频器和跨阻运算放大器（TIA）组成,该结构对于LTE多频带应用具有高集成,高线性,并实现简单的频率配置。电路采用多个电流舵跨导级实现了大的可变增益控制范围。电流型无源混频器采用25%占空比本振改善了电路增益、噪声和线性性能。为了抑制带外干扰,采用直接耦合电流输入滤波器。该射频前端电路采用0.13-μm CMOS工艺设计制造。测试结果表明电路在2.3GHz到2.7GHz工作频率范围,具有45dB电压转换增益,噪声系数为2.7dB,IIP3为-7dBm以及校准后的IIP2为 60dBm。电路采用1.2V单电压供电,整个电路工作电流为40mA。     

高性能的MIMO-OFDM接收机IQ不平衡补偿新算法

在分析MIMO-OFDM接收机IQ不平衡信号模型基础上,以OFDM物理层为背景提出了一种新的时频结合的MIMO-OFDM接收机IQ不平衡补偿算法,即先在时域对IQ不平衡预补偿,然后在频域对残余的IQ不平衡进行校正.仿真结果表明:本文所提算法性能优于传统的频域补偿算法,该算法在AWGN信道下能达到理想性能,在多径衰落信道下当误比特率等于10-3时性能损失可以减小到0.5dB左右.     

High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding

In electronic-warfare (EW) receiver applications, real-time measurement of the radar signals' carrier frequencies is mandatory and considered to be one of the most important radar parameters. Accurate frequency detection can be used to sort and deinterleave signals in a dense signal environment where multiple signals arrive simultaneously presenting severe problems unless they can be differentiated appropriately. Researchers and engineers are actively looking for new algorithms for high resolution wideband receivers with easier implementation. This paper presents an adaptive gain control and dynamic thresholding wideband digital receiver to accurately detect two simultaneous high dynamic range signals, even when their signal frequencies are very close. The proposed fast Fourier transform (FFT) based receiver examines incoming signal characteristics and provides real-time accomplishment of these tasks, by way of using an adaptive gain-control amplifier, a squarer, two analog-to-digital converters, and two FFT's. The wideband receiver offers high probability of intercept over wide instantaneous RF bandwidths, high dynamic ranges and sensitivity. Two simultaneous signal accommodations and their characteristics are provided to demonstrate the improvements over presently used receivers in this field.     

一种基于对消技术的瞬时大动态接收机

针对侦察系统的电磁环境适应性受限于其动态范围的问题,提出了基于对消技术的瞬时大动态接收机,以此来提高侦察系统的动态范围。分析了影响侦察系统动态范围的因素,提出了在固定一中频将同源信号中的强信号分离,并在数字域进行自适应处理,在模拟域内进行功率抵消的接收机构架,同时分析了影响对消比的因素。通过仿真验证了该技术的可行性,并指出该技术路线尚需解决的问题。     

A wide dynamic range receiver channel for a pulsed time-of-flightlaser radar

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed and tested. The bandwidth of the receiver channel is 170 MHz, the transimpedance can be controlled in the range from 1.1 kΩ to 260 kΩ, and the input-referred noise is ~6 pA/√Hz. The distance measurement accuracy is ±4.7 mm (average of 10000 measurements), taking into account walk error (input signal amplitude varies in the range 1:624) and jitter. A considerable increase in the input dynamic range of the receiver has been achieved by placing an integrated current buffer with variable attenuation between the external photodetector and the transimpedance preamplifier. Integrated electronic gain control structures together with the small size and low power consumption achieved by the use of full custom integrated technology considerably simplifies rangefinding devices for many applications. The circuit was implemented in an 0.8-μm BiCMOS process