氮气氛下衬底负偏压预溅射对GaAs肖特基势垒性能的改善

本文研究了不同气氛下衬底负偏压预溅射对GaAs肖特基势垒特性的影响。我们发现,采用氮气氛下衬底负偏压预溅射新工艺能明显改善GaAs肖特基势垒特性:势垒高度增高,势垒电容减小和二极管反向击穿电压增大。这种新工艺对于GaAs肖特基势垒特性改善和GaAs MESFETs性能提高是一个非常有用的技术。     

难熔金属氮化物栅的技术研究

本文采用衬底负偏压溅射方法对比研究了ZrN薄膜及其与GaAs的肖特基势垒特性,结果表明,该法不仅能降低ZrN薄膜电阻率,而且能增高GaAs肖特基势垒高度.文中还用不同剂量的氮离子对GaAs衬底进行注入实验,可以看出,氮注入明显地改善了Ti/n-GaAs肖特基势垒特性.     

GaAs/AlN异构集成太赫兹倍频器芯片

针对太赫兹GaAs肖特基二极管倍频器芯片散热能力差导致输出功率低的问题,开展了GaAs/AlN异构集成太赫兹倍频器芯片研究。通过稳态热仿真发现,将肖特基二极管芯片衬底由GaAs替换为热导率更高的AlN可以降低结温。对芯片衬底替换工艺开展了研究,获得了GaAs/AlN异构集成太赫兹二极管。分别对基于GaAs衬底二极管和基于GaAs/AlN异构集成二极管的162 GHz倍频器开展功率性能测试对比。测试结果表明:装配GaAs衬底二极管的倍频器输入功率为200 mW时,输出功率最高为43.6 mW;而装配GaAs/AlN异构集成二极管的倍频器输入功率提高到316 mW,输出功率为72.4 mW。肖特基二极管由GaAs衬底替换为AlN衬底后耐受功率(输入功率)提高了约58%,倍频效率由21.8%提升至22.9%,输出功率也相应提升,验证了相比GaAs衬底肖特基二极管,GaAs/AlN异构集成太赫兹二极管的散热性能及耐受功率具有明显的优越性。     

直流磁控溅射TiN/GaAs肖特基结的电学特性研究

本文研究了经直流磁控溅射制备的TiN/GaAs肖特基结的电学特性.给出了不同退火温度下I-V,C-V测量结果及TiN/GaAs与Au/GaAs,Ti/GaAs,Al/GaAs接触特性的比较.应用AES与XPS进行肖特基结的表面和界面剖析,发现退火过程中TiN膜的氧化,N在TiN膜中的再分布及TiN-GaAs接触界面上的化学重组对肖特基结的接触特性有重要影响.     

TiSi_x/GaAs肖特基接触的退火特性

本文对用分层电子束蒸发法形成的TiSi_x/GaAs的肖特基接触特性进行了研究,分析了不同组分下经快速退火和常规退火后TiSi_x的电阻率,与GaAs接触界面的热稳定性,化学稳定性及所形成肖特基结的电特性.结果表明:TiSi_21/GaAs界面在975℃、12秒快速退火下表现出好的热稳定性和化学稳定性,所形成的肖特基接触具有良好的电特性,在800℃、20分钟的常规退火下,界面处有Ti的堆积和某种界面化学反应.对于快速退火工艺,TiSi_2可满足作为自对准 GaAs MESFET栅极材料所要求的界面稳定性.     

GaAs/Pt-W-Pt-Au势垒

本文详细地介绍了制备X波段的GaAs雪崩二极管的肖特基势形成方法。通过严格清洗n型GaAs外延片,合理地溅射淀积多层金属Pt-W-Pt-Au形成的势垒,特性良好,有效地改善了GaAs功率雪崩二极管的性能。     

砷化镓肖特基势垒光电二极管

美国某公司试制成带宽为100千兆赫的平面型砷化镓(GaAs)肖特基势垒光电二极管.基片是平面的半绝缘性GaAs,在它上面用液相外延法形成0.4微米厚的N~+GaAs层和0.3微米厚的NGaAs层.NGaAs层的自由电子密度为1×10~(17)/厘米~3;对肖特基势垒和     

GaAs表面Ga、As的比对GaAs MESFET击穿电压的影响

通过用XPS分析GaAs MESFET肖特基势垒制作前后的表面情况,发现GaAs表面Ga、As的比,对GaAs MESFET击穿电压有着明显的影响,表面Ga、As比的明显偏离将导致击穿电压的下降.分析了GaAs表面Ga、As比偏离的原因,提出了改进的方法.     

自对准钨栅GaAs MESFET IC工艺

为了制备耐高温肖特基势垒,已采用RF或DC磁控溅射法在n~+n型GaAs衬底上溅射淀积钨(W)膜。这种膜具有良好的力学及电学性质。膜的可蚀性及肖特基势垒的热稳定性能够满足自对准栅IC的要求。新颖的自对准结构及用W栅制成的自对准离子注入GaAs MESFET初步特性能说明W栅工艺适用于GaAs IC。     

ZrN/n-GaAs肖特基势垒特性研究

本文用RBS,AES和电特性测量等方法,研究了ZrN/n-GaAs肖特基势垒.结果表明ZrN/GaAs势垒有良好的电特性和高温稳定性.经850℃高温退火后,势垒高度为0.90eV,理想因子n=1.02.同时我们观察到,随着退火温度升高(从500℃升高到850℃),ZrN/GaAs势垒电特性有明显改进:肖特基势垒高度增大、二极管反向电流减小、二极管电容减小和反向击穿电压增大.以上特点表明,ZrN/GaAs是用于自对准高速GaAs集成电路的较为理想的栅材料.     

Study of Ti/W/Cu,Ti/Co/Cu,and Ti/Mo/Cu multilayer structures as schottky metals for GaAs diodes

Schottky structures with copper and refractory metals as diffusion barrier for GaAs Schottky diodes were evaluated. These structures have lower series resistances than the conventionally used Ti/Pt/Au structure. Based on the electrical and material characteristics, the Ti/W/Cu and Ti/Mo/Cu Schottky structures are thermally stable up to 400°C; the Ti/Co/Cu Schottky structure is thermally stable up to 300°C. Overall, the copper-metallized Schottky structures have excellent electrical characteristics and thermal stability, and can be used as the Schottky metals for GaAs devices.     

LaB_6/GaAs肖特基势垒研究

用电子束蒸发LaB_6单晶的方法,制备了LaB_6/GsAs肖特基势垒,经800℃高温退火后,势垒高度为0.70eV,理想因子为1.15～1.2。用俄歇能谱观察到LaB_6/GaAs界面有良好的热稳定性,以LaB_6为栅得到了初步的全离子注入的MESFET特性。结果表明,LaB_6有希望用于GaAs集成电路。     

Structural characterization of Ti and Pt thin films on GaAs(100) substrate

In an attempt to understand the Schottky barrier behavior of Ti/Pt/GaAs and Pt/Ti/ GaAs bimetal Schottky diodes, we have investigated the interfacial morphology of Ti and Pt thin films on GaAs(l00) substrate. The characterization was based on coverage profiling of Auger electron spectroscopy in conjunction with transmission electron microscopy. Emphasis was placed on film uniformity and atomic interdiffusion. The results showed Ga and As outdiffusion in Pt/GaAs interface and some oxygen incorporated in Ti film, but no evidence of clustering for both metal/GaAs systems.     

Fabrication technology of stable Schottky barrier gates for gallium arsenide MESFETS

An improved structure for stable GaAs Schottky gates formed by the lift-off technique is described. Schottky gates made by the lift-off process often have an interfacial layer and resulting MESFETS have unsatisfactory characteristics. To obtain a transfer characteristic unaffected by the interfacial layer, using rhodium for the contacts is effective. In the case of nickel Schottky contact with interfacial layer, MESFET transfer characteristics are improved by annealing the contact. The Ni film for the contacts consumes GaAs corresponding to its thickness during alloying. To reduce the consumption of GaAs, a thin Ni film should be used.     

High temperature annealing behaviour of Schottky barriers on GaAs with gold and gold-gallium contacts

It is shown that unlike AuGaAs Schottky diodes, a Schottky barrier made on GaAs using an evaporated film of AuGa eutectic alloy does not degrade on heat treatment. It is shown that the presence of Ga in the top contact prevents micro-alloying to take place during heat treatment and thus prevents degradation of the diode behaviour.     

Controlled diode profiling for GaAs strip-coupled correlators

Surface acoustic wave (SAW) memory correlators employ the varactor properties of Schottky diodes arrayed along the acoustic path. Described, and illustrated, here is a tailoring of the implant which defines the Schottky diode region of the strip-coupled GaAs surface acoustic wave memory correlator. The new implant schedule has resulted in improvements in correlation efficiencies in the range of 10-15 dBm for these devices compared to previously reported strip-coupled GaAs memory correlators.     

Electrical characteristics of GaAs MIS Schottky diodes

The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of GaAs metal-insulator-semiconductor (MIS) Schottky barrier diodes are investigated over a wide temperature range and compared with MS diodes. The effects of the insulating layer on barrier height and carrier transport are delineated by an activation energy analysis. Excess currents observed at low forward and reverse bias have also been analyzed and their cause identified. A capacitance anomaly consistently noticed in MIS Schottky barriers is resolved by stipulating a non-uniform interfacial layer, and a self-consistent model of the GaAs MIS Schottky barrier is developed by analyzing I-V and C-V data of both MIS and MS diodes.