ATM交换网络的实现方案

本文主要介绍了实现ＡＴＭ交换网络的三种交换结构，并阐述了其各自的优缺点。此外，对于共享存储器交换结构，笔者还提出了复制的概念，以双端口的冗余配置换取了存储器的存取时间。     

基于UX8交换芯片的机群互连网络设计

构造机群系统的互连网络要求具有高带宽、低延时、高可靠及容错等特性，而实现这些特性的关键是实现网络连接的交换部件和网络适配器。文章介绍了8端口交换芯片UX8和网络适配器的设计和实现方法，交换芯片采用虫洞路由流量控制方法减少对缓存空间的需求，切入交换机制减小数据包传送延时，同步信号传送方式提高了链路上的信号传送速率，源址路由方式支持任意拓扑结构的网络，FPGA实现表明其单端口单向带宽可达到1．6Gbit／s，延迟时间为240ns。网络适配器内含Intel公司的i960VH处理器作为通信处理机，在以DMA方式工作时，测得点到点数据传送带宽可达506Mbit／s。     

基于时频二维竞争解决机制的光数据包交换节点性能分析

针对光数据包交换的应用需求,提出了基于时频二维竞争解决机制的光数据包交换节点结构,建立了该节点基于排队论的丢包率分析模型,分析讨论了光交换节点竞争解决机制对丢包率的影响。输出端口归一化负载为0.8时,时频二维竞争解决机制在8波复用和8根延迟线结构下使丢包率降低至约10-7。数值分析结果表明,高端口负载下增加复用波长个数对减小端口丢包率比较有效,低端口负载下增加FDL延迟线数量对减小端口丢包率比较有效。     

VOQ输出端解复用算法及其技术实现

目前的高速交换机大都采用虚拟输出排队(VOQ)方法,并把变长分组拆成定长信元后交换。已有的关于队列组织与管理的文章都着重于讨论N×N交换结构中每个端口对应于一个实际物理端口的情况,但在实际中经常需要对端口进行复用和解复用。我们针对863“实用化综合接入系统”边缘路由器子系统的设计特点,自行提出了基于输出子端口的队列组织与解复用算法。这篇文章阐述了该算法,并给出了算法的性能分析和具体实现。     

DOCSIS3.0——第三代电缆数据传输系统(3)

第三节数据转发一、什么是转发,转发和交换的差别通信系统最主要的作用是数据的交换,交换的英文名称为Switching。例如以太网交换机,其最主要的功能是将从一个端口输入的数据包打开,找出目的地址,按路由规则,将这个数据包送到相应的端口上,即所谓交叉连接。数据包本身的格式并没有改变,即通     

Clos网络中变长分组交换及调度算法研究

Clos网络是多端口的路由器和交换机中经常采用的交换网络,其优点在于它是一个结构全对称的网络。比较了多级Clos网络分布式调度算法中定长分组和变长分组交换的特点;给出一种基于变长分组交换的MSM型三级Clos交换网络结构和相应的ACBS调度算法;消除了分组负载分配的不公平性。分析表明该调度算法优于传统算法,并通过仿真实验验证了算法的有效性。     

基于SRAM的核心路由器交换矩阵输入端口设计

交换矩阵是核心路由器的重要组成部分,为了避免来自不同输入端口的信元同时发往同一个输出端口,需要在输入端口设置缓冲区,即输入排队交换结构。基于静态随机存储器完成了交换矩阵输入端口虚拟输出队列（VOQ）的设计,该设计可以降低核心路由器交换芯片的面积,提高输入端口缓冲区信元的响应速率,并通过DE-115开发板完成对设计的验证。     

一种新型可扩展的多级多平面分组交换结构的图论模型与性能分析

该文提出了一种新型可扩展的多级多平面(MPMS)分组交换结构。首先建立了MPMS的图论模型,定量地描述了MPMS中相邻连通性和端口可达性,定义了MPMS的均衡顶点和竞争顶点,并证明了MPMS决定交换性能的输入端口与输出端口间的无阻塞条件。从性能参数和结构复杂度等方面与单级交叉开关做了对比分析,结果表明MPMS可以获得P倍的最大端口速率,平方倍的最大端口数,线性比例增长的结构复杂度,具有良好的可扩展性。     

分组交换技术在光传输网中的研究与设计

针对用电路交换技术传输OTN信号面临容量、速率受限的问题,研究了基于包结构的光传送网的优势并提出实现方案。文中首先介绍了分组交换网络和光传送网相结合的基本结构,以及OTN帧结构及混合网络中标准的包格式,最后描述了一个将OTN技术和数据包技术相融合的可实现结构。该结构能将光信道数据单元解复用为低阶形式,并将其切割为离散的数据包。切割好的数据包由标准包接口送往包交换芯片进行交换,交换后的数据包进入重组模块,将其重组为连续的数据流,再由复用模块将光信道数据单元复用到其高阶形态发送出去。     

简讯

中兴通讯推出系列电信级高端路由器产品 最近,在第十届上海国际信息通信展上,中兴通讯展示了其自主开发的国内第一个全系列的真正具备产业化能力的高端路由器──中兴 ＺＸＲ１０－ ＴＳＲ电信级高端路由器。 ＺＸＲ１０- ＴＳＲ采用先进的模块化结构和统一的系统软件平台,在交换容量、端口速率、端口密度及包转发能力等方面都处于国内领先的地位。该系列产品在系统的分布式处理能力、协议的支持能力等方面远远超过部分以普通ＡＴＭ交换机包装成的“高端路由器”产品。与传统路由器采用软件来转发数据包不同的是,ＺＸＲ１０－ＴＳＲ是通…     

Scheduling scheme using Look-ahead Buffer and Loop-back Buffer in Two-stage variable optical packet switch

Programmable variable delay lines have been developed, so as to delay packets in variable durations by combining several lengths of Fiber Delay Lines (FDLs) in optical packet switch. In practice, Two-stage variable optical packet switch with this programmable variable delay lines has been proposed. This switch has two buffers. The one is the programmable variable delay lines (Look-ahead Buffer). The other is the fixed FDLs that re-input a packet from the output to the input (Loop-back Buffer). The switch can foresee following packets and avoid contentions effectively by using two buffers. However, existing studies only focus on the Look-ahead Buffer. Intelligent usage of the Loop-back Buffer is actually out of concern. This paper proposes a sophisticated scheduling method in the Two-stage switch. The proposed method controls both the Look-ahead Buffer and the Loop-back Buffer cooperatively and improves the utilization of the switching process. The proposed method uses the Loop-back Buffer adaptively and distributes traffics in time and space domain. The effectiveness of the proposed method is evaluated through extended simulation experiments and basic hardware design.     

基于GPRS的IP电话技术研究

文章研究了一种的新的无线IP电话技术GPRS-VoIP,是一种基于GPRS接入的IP电话技术,可以实现和传统的基于电路交换的语音通话进行无缝切换.文中分析了该技术下的通话和传统GSM语音通话的无缝切换.文中还详细的分析了时廷、丢包、通话不连续等因素对基于GPRS接入的IP通话的影响和其对于带宽的需求,并提出了相应的解决方法.     

一种输入输出排队交换机中分布式分组调度方法的研究

针对采用共享缓存(shared memory)做为交换机构(switching fabric)的输入输出排队交换机,该文给出了一个分布式分组调度方法DHIOS(Distriduted Hierarchical Ingress and OutputScheduling)并做了详细的仿真。表明DHIOS可以支持变长分组,能够确保业务流的QoS,性能优良。     

Performance analysis of the ATM shuffleout switch under arbitrarynonuniform traffic patterns

Shuffleout is a blocking multistage asynchronous transfer mode (ATM) switch using shortest path routing with deflection, in which output queues are connected to all the stages. This paper describes a model for the performance evaluation of the shuffleout switch under arbitrary nonuniform traffic patterns. The analytical model that has been developed computes the load distribution on each interstage link by properly taking into account the switch inlet on which the packet has been received and the switch outlet the packet is addressing. Such a model allows the computation not only of the average load per stage but also its distribution over the different links belonging to the interstage pattern for each switch input/output pair. Different classes of nonuniform traffic patterns have been identified and for each of them the traffic performance of the switch is evaluated by thus emphasizing the evaluation of the network unfairness     

网管软件主备切换协议的设计和验证

软件系统的主备切换功能可以保证系统的高可靠性。该文设计了一种简单的主备切换协议,提供了主备切换协议中的帧设计,描述了该协议在启动监控和执行监控切换时的状态,以及自动切换和手动切换的情况。并将这一功能应用于网络管理软件,有效降低了丢包率,提高了系统的可靠性。最后对该协议进行了验证。     

A Knockout Switch for Variable-Length Packets

The Knockout Switch is a new packet switch architecture recently proposed for high-speed local and metropolitan area networks, multiprocessor interconnects, and local or toll switches for integrated traffic loads. We describe an approach to extend the original Knockout Switch to work with variable-length packets. This new architecture employs an input broadcast bus arrangement to achieve complete interconnection of the inputs and outputs. Consequently, there is no congestion in the switch fabric other than the unavoidable conflict of multiple simultaneous packets destined for the same output. It is with this output contention that the Knockout principle is fully utilized to efficiently concentrate and store contending packets while maintaining the first-in first-out discipline of the packet sequence; and yet the fabric speed required is no more than the input/output line speeds, Under these design goals, no switch can yield better delay/ throughout performance. These are the most important attributes that have been preserved in the current proposal from the original Knockout Switch. For anN times Nswitch configuration, the variable-length packet Knockout Switch consists ofNinput broadcast buses, and anN:Lconcentrator (L ll N) and a shared buffer for each output. The design of each subsystem is discussed with emphasis on possible VLSI realization. Using today's technology, we should be able to implement the proposed switch with both input/output lines and internal hardware operating at 50 Mbits/s. The dimension of the switch (N times N) can grow modularly from say 32 × 32 to 1024 × 1024, rendering a total throughput in the range of tens of gigabits per second. Future upgrading of the line interfaces to much higher speed without modification to the internal switch hardware is also possible with a modest restriction on the minimum length of new packets.     

Third generation WCDMA radio evolution

Third Generation Partnership Project (3GPP) produced the first full version of the WCDMA standard at the end of 1999. This release, called Release'99, contains all the necessary elements to meet the requirements for IMT‐2000 technologies, including 2 Mbps data rate with variable bit‐rate capability, support of multi‐service, QoS differentiation and efficient packet data. The Release 5 specifications were created in March 2002 and they contain downlink packet data operation enhancement, under the title high speed downlink packet access (HSDPA). HSDPA utilizes Hybrid ARQ and higher order modulation for improving data‐spectral efficiency and for pushing bit rates beyond 10 Mbps. The further 3GPP releases will study the enhancements of packet‐data performance in uplink. Other important features in future 3GPP releases include advanced antenna technologies and WCDMA standard for new spectrum allocations. The paper describes the main solutions of 3GPP WCDMA standard in more detail. Copyright © 2003 John Wiley & Sons, Ltd.     

On the speedup required for a multicast parallel packet switch

A parallel packet switch (PPS) is a switch in which the memories run slower than the line rate. Arriving packets are load-balanced packet-by-packet over multiple lower speed center stage packet switches. It is known that, for unicast traffic, a PPS can precisely emulate a FCFS output-queued (OQ) switch with a speedup of two and an OQ switch with delay guarantees with a speedup of three. In this paper we ask: is it possible for a PPS to emulate the behavior of an OQ multicast switch? The main result is that for multicast traffic an N-port PPS can precisely emulate a FIFO OQ switch with a speedup of S>2√N+1, and a switch that provides delay guarantees with a speedup of S>2√(2N)+2     

Next generation routers

As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capacity (e.g., multipetabit). This paper first points out the issues of building such routers, such as memory speed constraint, packet arbitration bottleneck, and interconnection complexity. It then presents several algorithms/architectures to implement IP route lookup, packet classification, and switch fabrics. Some of the functions, such as packet classification, route lookup, and traffic management, can be implemented with emerging network processors that have the advantages of providing flexibility to new applications and protocols, shortening the design cycle and time-to-market, and reducing the implementation cost by avoiding the ASIC approach. Several proposed algorithms for IP route lookup and packet classification are compared in respect to their search/update speeds and storage requirements. Different efficient arbitration schemes for output port contention resolution are presented and analyzed. The paper also surveys various switch architectures of commercial routers and switch chip sets. At the end, it outlines several challenging issues that remain to be researched for next generation routers     

Gigabit Ethernet switches using a shared buffer architecture

Gigabit Ethernet networks have seen great demand in recent years. This growth was fueled by both an increase in port speed at the client side and new applications in MAN and WAN space. In this article, we report a highly integrated Ethernet switch IC design that supports 12 gigabit ports and one 10 Gb port. All packet memory and search memory are integrated on chip. A deeply pipelined structure with parallel memory access is employed to achieve wirespeed search performance. A flexible policy engine is designed to allow packet filtering and modification. A novel tail buffer architecture is proposed to address the variable packet length issue in the shared buffer architecture. Custom mixed-signal circuits are incorporated to implement the 10G Ethernet interface in XGMII. The chip integrates 70 million transistors in a 16 mm /spl times/ 15 mm die using 0.18 /spl mu/m CMOS technology. The chip has been tested to verify the wirespeed searching and switching performance.