A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A rail-to-rail CMOS op amp

A CMOS op amp (operational amplifier) is reported which has a rail-to-rail voltage range at its input as well as its output. An area-efficient output stage has been used. While the entire op amp occupies only 600 mil², when used as a unity-gain buffer and with ±5-V supplies, the op amp can drive a 9-V_pp/1-kHz sine wave across a 300-Ω load with -64 dB of harmonic distortion     

1 V rail-to-rail constant-gm CMOS op amp

A 1 V rail-to-rail constant-g_m CMOS operational amplifier is proposed. This study shows that keeping the sum of currents in the complementary differential pairs constant rather than controlling the tail currents produces a constant-g_m input stage operating in the weak inversion. The currents in the n-channel differential pair are regulated to keep the sum of currents in the complementary differential pairs constant using a negative feedback loop. This study also provides experimental results obtained from a 0.35 μm CMOS prototype chip.     

A rail-to-rail input/output CMOS power amplifier

A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common-mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed. The circuit, which measures only 0.3 mm² in a 3-μm technology, has a quiescent current consumption of 600 μA and a CMRR larger than 55 dB. It handles up to 4 nF, and can, with a 5-V supply, drive 3.8 V_pp into 100 Ω (0.1% total harmonic distortion at 10 kHz)     

CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage

Two 3.3-V operational amplifiers with constant-g _m rail-to-rail input stage and rail-to-rail output stage are presented. The constant transconductance (g _m ) ensures a constant unity-gain frequency within the whole commonmode input range. Two new methods to control theg _m are introduced. Both operational amplifiers use the same rail-to-rail output stage. The operational amplifiers have been integrated in a CMOS semicustom process with transistor lengths of 10µm. The common-mode input voltage swing extends beyond the positive supply rail by 400 mV and beyond the negative supply rail by 200 mV. The output voltage is able to reach within 130 mV of the supply rails. The output current of the operational amplifiers is 2 mA and the voltage gain is 85 dB. The unity-gain frquency is 165 kHz, which is mainly limited by the relatively long transistor lengths of 10µm. In another process with channel lengths of 2µm, simulation results showed that a unity-gain frequency of 4 MHz can easily be obtained.     

A self-terminating low-voltage swing CMOS output driver

A CMOS output pad driver circuit is described that automatically series-terminates a driven line in the line's characteristic impedance. The circuit has advantages in speed, power, and size over conventional designs. The key idea is the use of emitter-coupled logic (ECL) compatible low-voltage swings for signaling, combined with the use of the driver transistor as both a switch and as a termination resistor. An on-chip measurement circuit dynamically adjusts the impedance of the driver to match the impedance of an external reference impedance standard, allowing the circuit to compensate for both chip and board level fabrication variations     

An integrated low-voltage class AB CMOS OTA

We present a new circuit topology for a low-voltage class AB amplifier. The circuit shows superior current efficiency in the use of the supply current to charge and discharge the output load. It uses negative feedback rather than component matching to optimize current efficiency and performance, resulting in a current boost ratio exactly equal to one. Measurement results for an example circuit fabricated in a 2-μm CMOS process are given. The circuit uses a quiescent supply current of 0.2 μA and is able to settle to a 1% error in 1.1 ms for a 0.4-V input step and a load capacitance of 35 pF. The circuit design is straightforward and modular, and the core circuit can be used to replace the differential pair of other op-amp topologies     

A low-voltage BiMOS op amp

Describes the development of a threshold implanted BiMOS amplifier IC optimized for 2-5 V operation at a supply current of 300 /spl mu/A. A nonlinear operational transconductance amplifier (OTA) buffer having on-chip feedback provides a low-impedance rail-to-rail output, and a bulk-modulated PMOS input pair extends the common-mode range. Protective-network bootstrapping makes possible subpicoampere input-bias currents below 85/spl deg/C, and improved offset stability is achieved by the choice of threshold-level stage currents. Amplifier design is straightforward and readily applied from `micropower' to `broad-band' operating ranges. The combination of these features has produced a unique high-performance integrated circuit.     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

Very low-voltage class AB CMOS and bipolar precision currentrectifiers

Simple class-AB CMOS and bipolar precision rectifier circuits that operate from a single supply close to a transistor's threshold voltage are introduced. These circuits have output voltage swings comparable to the supply voltage. Results from simulations of MOS and bipolar precision rectifiers at 20 and 100 MHz, respectively, are presented. Experimental results of a test chip are presented that verify the proposed circuits. A full wave precision rectifier based on the proposed rectifier cells is discussed     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Input switch configuration suitable for rail-to-rail operation ofswitched op amp circuits

A switch configuration to be used at the input of switched op amp circuits is introduced. The circuit is an extension of the gate-source bootstrapping technique such that rail-to-rail operation of the input switch becomes possible. Simulations show the usefulness of the proposed circuit down to 0.9 V     

Current mode instrumentation amplifier with rail-to-rail input and output

This paper presents the results from an investigation on the implementation of Current Mode Instrumentation Amplifiers (CMIAs) with rail-to-rail operational amplifiers (op amp) with a gm control circuit. The objective of employing rail-to-rail op amps in the implementation of a CMIA is the improvement of the common-mode operation range. The enhancement of the input common mode range (ICMR) is obtained using op amps with a rail-to-rail input stage followed by a cascode-based output stage. A prototype of the CMIA was implemented in standard 0.6 μm XFAB CMOS technology. Test results showed that the CMIA common mode range was extended but with moderated CMRR. To minimize this issue the amplifier was re-designed and sent to fabrication. Simulations with the components variations included were performed and showed the enhancement of the CMRR can be expected.     

Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

Constant-gm rail-to-rail CMOS op-amp input stage withoverlapped transition regions

Conventional techniques to achieve a constant-g_m rail-to-rail complementary N-P differential input stage require complex additional circuitry. In addition, the frequency response and common-mode rejection ratio (CMRR) are degraded. An economical but efficient design technique to overcome these problems is proposed. The proposed technique strategically overlaps the transition regions of the tail currents for the n- and p-pairs to achieve constant overall transconductance. Experimental results demonstrate that g_m variation can be restricted to within ±4% with improved CMRR and frequency response     

Low-voltage constant-gm rail-to-rail CMOS operational amplifier input stage

This paper presents a rail-to-rail constant-g_m operational amplifier input stage. The proposed circuit changes the tail current of the input differential pairs dynamically for a constant-g_m by using dummy input differential pairs. The problem which causes total g_m variation is input pairs and dummy input pairs can not take effect at the same time with the common-mode input voltage changes, because the tail current transistor of the input pairs are in triode region when the input pairs are turned off, the dummy input pairs will enter subthreshold region from cut-off region before the input pairs when common-mode voltage changes. The effect of this problem is more obviously in low supply voltage design. To solve this problem, compensate current sources is added to the tail current transistors of each dummy input differential pairs for lower g_m variation. The g_m of this Op Amp’s input stage varies around ±2%.     

1-V operational amplifier with rail-to-rail input and output ranges

A bipolar operational amplifier (OA) with rail-to-rail input and output ranges which can operate at supply voltages down to 1 V is presented. At this supply voltage, the input offset voltage is typically 1.0 mV in an input common-mode voltage range that extends beyond both supply rails for about 300 mV, with a common-mode rejection ratio (CMRR) between 38 and 100 dB, depending on conditions. The output voltage can reach both supply rails within 100 mV, the output current is limited to ±10 mA, the voltage gain is 100 dB, and the bandwidth is 450 kHz. The die is 2.5×5.5 mm². Qualities such as offset, input-bias current, and CMRR are improved when the supply voltage is increased and the dynamic level shift is autonomically turned off. The OA has been protected against unintentional reversal of the output signal when the inputs are substantially overdriven. The output stage of the circuit consists of two full complementary composite transistors, whose HF characteristics have been improved by internal Miller compensation and linearization of the transconductance     

New input/output designs for high speed static CMOS RAM

New input and output schematics and optimum design for cell and array are proposed, and applied to a 256/spl times/4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5 /spl mu/m layout rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation.