一种适合测距应用的数字相位跟踪测量环性能分析

本文介绍了一种新型数字相位跟踪测量环(DPTML)结构,并应用有限状态Markov链理论求解其稳态误差和响应时间.通过分析关键部件的抗噪声性能给出了参数选择依据,提出了应用稳态结果进一步降低输出误差的"稳态平均法".计算和仿真结果均表明,该DPTML比传统的过零采样数字锁相环(ZC-DPLL)具有更强的抗噪声性能,并有效消除了高信噪比下的"hangup"效应,缩短了响应时间,更适于测距应用.     

相位量化DRFM的误差性能分析

相位量化数字射频存储器(DRFM)由于具有结构简单、存储量小、动态范围大等优点得到了广泛的关注。该体制DRFM是对雷达信号的相位瞬时值进行量化,其相位误差会对DRFM的性能产生影响。针对相位量化DRFM中由于量化位数有限和信号存在噪声引起的量化、噪声相位误差进行分析,推导出相位误差的概率密度函数。最后对3bit相位量化DRFM的相位误差进行了仿真分析。     

相位比较器CH5081应用三例

CH5081系CMOS集成电路,它内含一个数字相位比较器和一个单独的反相器,电路如图1所示。(CH5081的工作原理可参阅本刊1990年第6期有关文章)。 CH5081适用于通信、仪器仪表及自动控制等诸多领域的应用,本文介绍三个实例。一、相位计 CH5081具有对不同频率的数字信号进行相位比较的功能。当两路脉冲信号分别从R和S端输入时,CH5081内含的数字相位比较器就对输入脉冲上升沿的相位进行比较,并从脚3和脚4输出比较的结果。在两路输入信号的相位超前、滞后和一致时,输出信号     

全数字接收机中一种载波相位恢复的新方法

全数字接收机是在最近几年内提出的一个新的概念,它要求解调用的本地参考载波和采样时钟都振荡于固定的频率,不需要进行反馈控制,其他一些工作:载波相位误差和时钟定时误差的消除、信号的判定等全部由采样后的数字信号处理器完成。载波相位恢复问题和时钟同步问题是目前关于全数字接收机研究中的两个最主要的问题。本文仅讨论载波相位恢复问题。在本文中研究了载波相位估计算法中估计e~(jθ)和估计θ的差异,从理论上证明了估计e~(jθ)比估计θ有更好的统计特性,并且给出了一种估计e~(jθ)的方法,此方法有二个突出的优点:(1)它可以消除载波相位恢复过程中的相位区间跳变。(2)相位估计器的结构简单,它是全线性的,易于实现。利用16-QAM信号进行计算机仿真证实了此算法的可行性。     

相位量化数字射频存储器的寄生信号性能分析

本文导出了相位量化数字射频存储器的寄生信号性能。其寄生信号幅度随谐波次数的增加单调减小,峰值寄生信号为2~m-1次谐波(其中m为量化位数),其幅度为(2~m-1)~(-1),而近区(峰值寄生信号之前各次谐波)的寄生信号幅度为零。     

基于DDS的低相噪频率综合源设计

分析了相位累加器截断、波形ROM有限字长、DAC等对直接数字频率合成器(DDS)相位噪声的影响，得出了DDS芯片本身对输出信号相位噪声影响很小的结论。给出了采用AD9854芯片构成的低相噪频率综合源的硬件组成以及系统实测的相位噪声、杂散技术指标。     

宽带线性调频信号的性能检测方法

宽带线性调频频率源设计完成后,需要检测频率源的性能,解决检测过程中遇到的问题,提出一套工程上适用的宽带线性调频信号的性能检测方法。首先,根据相位残差曲线(测试信号与理想信号的相位差)的形状对匹配滤波器参数(主要是调频斜率)定性调整,能够快速得到最佳的脉冲压缩结果。然后从数学上证明这种方法的正确性。最后应用数字相位补偿的方法进一步提升宽带调频信号的脉冲压缩性能。实验证明,后期的数字补偿方法对非理想线性调频信号的压缩结果有较大的改善作用。文中测试数据来源于自行研制的频率源产生的1GHz宽带线性调频信号。     

数字信号处理在雷达相噪测量中的应用

随着通信和雷达的发展,脉冲信号的相位噪声成了影响整个系统性能的重要因素之一,采用传统模拟相位检波法测量脉冲信号相位噪声是一个非常大的挑战,因为这样的测试系统非常复杂,并且在测量相位噪声之前需要非常繁琐的校准程序,先进的正交数字相位解调和幅度解调技术能很好地解决这个问题。采用正交数字相位解调和幅度解调技术的系统不需要相位检波器和复杂的校准程序,利用极低噪声的参考源和互相关技术,提高了系统动态范围和测量灵敏度,实现了一键式精密测量脉冲相位噪声和调幅噪声。     

基于CORDIC算法的数字瞬时测频

数字瞬时测频(DIFM)是现代雷达对抗中的关键技术之一,它要求在极短的时间要完成对输入信号频率的测量。传统的瞬时测频方法是将频率信息转化为相位信息,之后再把相位信息转化为幅度信息,通过对幅度信息的量化编码,从而得到输入信号的频率。文中提出的是基于下变频,CORDIC算法的相位计算和相位推算法的数字瞬时测频方法。CORDIC算法的相位计算避免了乘法器的使用,因此适合实际应用。通过仿真得知,该方法对于单频信号的频率测量精度高,瞬时性好的优点,特别适合现代电子战接收机数字瞬时测频的需求。     

分布反馈光纤激光水听器相位一致性的测试方法

在传统压电水听器相位一致性测试的基础上提出了分布反馈(DFB)光纤激光水听器相位一致性的测试方法,并搭建了测试系统.采用偏振无关的非平衡迈克尔逊干涉仪和归一化的相位载波(PGC)解调方案,解调出光纤激光水听器感受的水声信号,并与参考压电水听器作对比,使用高精度相位检测器将两信号转化为相位差信号:重复测量第二支光纤激光水...     

The Limit-Switched Loop: A Phase-Locked Loop for Burst Mode Operation

In a time-division or burst mode communications systems, synchronization must be achieved within a short preamble time at the beginning of each burst. When used in such a system, a conventional phase-locked loop (PLL) occasionally exhibits a prolonged phase acquisition transient. This effect, known as hangup, occurs at a large value of phase error and may cause loss of a data burst. The present paper investigates a modification of a PLL known as a limit-switched loop (LSL). The LSL offers faster phase acquisition and better hangup immunity than a PLL. The LSL estimates its position in the phase plane at the beginning of acquisition and, if hangup is about to occur, makes a phase correction so as to forestall its occurrence. The structure and properties of the LSL are investigated in this paper.     

Fast timing recovery for linearly and nonlinearly modulated systems

Digital phase lock loops (PLLs) are often used in timing acquisition systems. It is known that some non-data-aided timing error detectors occasionally cause hangup problems in digital PLLs. In this paper, we introduce a novel two step antihangup timing recovery scheme. Through intensive simulations, we show that this enhanced scheme greatly reduces the probability of hangup, and speeds up the timing recovery process for both linearly and nonlinearly modulated systems.     

Hangup in Phase-Lock Loops

A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null. Restoring force is small in the vicinity of the reverse null, and noise causes the loop to equivocate about the null. Hangup is very troublesome when fast acquistion is needed with high reliability. One example is synchronization of digital communications. Hangups can be avoided if a large restoring force is applied for large phase errors and if equivocation is prevented. An implementation of an antihangup circuit is proposed.     

A novel U-turn counting hangup detection algorithm for SDPSKmodulation

A new hangup detection algorithm for symmetric differential phase-shift keying (SDPSK) modulation is proposed. Hangup is detected by observing phase transition patterns in the received SDPSK signal trajectory. The average pull-in times with and without the proposed hangup detector are compared. Simulation results show that the proposed algorithm significantly reduces the average pull-in time when the initial timing error is near the unstable null. We also show that the proposed algorithm is very robust against carrier frequency offsets     

Differential pass-transistor logic

Differential pass-transistor logic (DPTL), which offers the noise immunity needed to use the unique switching properties of FETs in realizing switching network efficiencies, is discussed. CMOS DPTL offers significant power-delay product advantages over conventional CMOS logic for both 5-V and 3-V power supplies. These features are achieved by DPTL's fewer and smaller parasitic capacitances, which are the result of significantly lower device counts combined with emphasized usage of minimum-size, n-channel pass-transistors. Substantial benefits are also obtained by using DPTL with depletion and enhancement/depletion GaAs MESFET technologies. Experiments show that GaAs DPTL offers substantial power-delay-product reductions over conventional GaAs realizations. Compared to CMOS DPTL, GaAs DPTL consumes less power at very high frequencies, a consequence of the electronic properties of GaAs and the smaller signal swings used in emitter/drain (E/D) DPTL     

Design of submicrometer CMOS differential pass-transistor logiccircuits

The interaction between the architectural features of CMOS differential pass-transistor logic (DPTL) and the submicron process technology used to implement it are examined. Techniques that exploit the noise immunity associated with the DPTL architecture are presented to effectively enable signal-swing reductions that result in increased speed. The extent to which DPTL can benefit from this signal-swing/speed tradeoff is examined by investigating the impact of device scaling on DPTL operation. A novel DPTL buffer that enables the implementation of a single-phase clocking scheme and the exchange of signal swing for increased circuit speed is proposed. Experimental results are provided     

Hangup in asynchronous timing recovery loops

The effects of hangup in digital asynchronous timing recovery loops are investigated. It is demonstrated that delay quantisation in the interpolation filter exacerbates the problem of hangup. It is also noted that the effects of hangup are worse for the non-data aided (NDA) loops than they are for the decision-directed (DD) loops. This may preclude the use of the former in TDMA applications.<>     

用于锁相环快速锁定的鉴频鉴相器设计

针对鉴频鉴相器(PFD)的盲区现象对锁相环路的锁定速度的影响,设计了一种PFD结构,可以实现锁相环路的快速锁定。该结构在传统PFD的基础上,利用内部信号的逻辑关系进行逻辑控制,其输出特性呈现非线性;在输入相位差大于π时,抑制了复位脉冲的产生,避免了输入时钟边沿的丢失,有效消除了盲区,加快了锁相环的锁定速度。设计采用SMIC 0.18μm标准CMOS工艺,采用全定制设计方法对该PFD结构进行了设计、仿真分析和验证。结果表明,采用该PFD结构的锁相环,在400 MHz工作频率下锁定时间为2.95μs,锁定速度提高了34.27%。     

A "flying-adder" architecture of frequency and phase synthesis with scalability

Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.