共查询到20条相似文献,搜索用时 0 毫秒
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《Electron Device Letters, IEEE》2008,29(12):1332-1335
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《Electron Device Letters, IEEE》2007,28(5):392-394
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Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors 总被引:1,自引:0,他引:1
Chih-Yang Chen Jam-Wem Lee Shen-De Wang Ming-Shan Shieh Po-Hao Lee Wei-Cheng Chen Hsiao-Yi Lin Kuan-Lin Yeh Tan-Fu Lei 《Electron Devices, IEEE Transactions on》2006,53(12):2993-3000
The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced 相似文献
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Won-Kyu Lee Joong-Hyun Park Joonhoo Choi Min-Koo Han 《Electron Device Letters, IEEE》2008,29(2):174-176
We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n+ amorphous silicon (n+ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (VTH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm2/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P+ ions) in the channel reduced the VTH and increased the S value. 相似文献
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Chen C.-Y. Lee J.-W. Chen W.-C. Lin H.-Y. Yeh K.-L. Lee P.-H. Wang S.-D. Lei T.-F. 《Electron Device Letters, IEEE》2006,27(11):893-895
In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design 相似文献
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Chih-Yang Chen Ming-Wen Ma Wei-Cheng Chen Hsiao-Yi Lin Kuan-Lin Yeh Shen-De Wang Tan-Fu Lei 《Electron Device Letters, IEEE》2008,29(2):165-167
Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states. 相似文献
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HgTe nanocrystal-based thin-film transistors (TFTs) with Al2 O3 top-gate dielectrics were fabricated on glass substrates using sintered HgTe nanocrystals as the channel layers. To the best of our knowledge, this is the first report on the fabrication of nanocrystal-based TFTs on glass substrates. Colloidal HgTe nanocrystal films were first formed on the glass substrates by spin-coating. The HgTe nanocrystal films were then sintered at 150 degC, leading to a dramatic increase in their conductance, compared with the as-deposited films. The TFTs fabricated in this letter exhibit the typical characteristics of p-channel transistors with a field-effect mobility of 1.04 cm2/Vmiddots, a threshold voltage of +0.2 V, and an on/off current ratio of 1times103. These results suggest that spin-coating and sintering at a low temperature enable the simple and low-cost fabrication of nanocrystal-based TFTs on glass substrates 相似文献
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Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors 总被引:2,自引:0,他引:2
Hsing-Huang Tseng Tobin P.J. Kalpat S. Schaeffer J.K. Ramon M.E. Fonseca L.R.C. Jiang Z.X. Hegde R.I. Triyoso D.H. Semavedam S. 《Electron Devices, IEEE Transactions on》2007,54(12):3276-3284
Using a fluorinated high-k/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-k deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated TainfinCy/HfZrOinfin/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon. 相似文献
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《Electron Device Letters, IEEE》2008,29(11):1222-1225
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《Electron Device Letters, IEEE》2009,30(1):33-35
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《Electron Devices, IEEE Transactions on》2009,56(4):587-594
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以非晶硅为晶化前驱物,采用镍盐溶液浸沾的方法可以得到超大尺寸碟型晶畴结构的低温多晶硅薄膜.所得多晶硅薄膜的平均晶畴尺寸大约为50 μm,空穴的最高霍尔迁移率为30.8 cm~2/V·s,电子的最高霍尔迁移率为45.6 cm~2/V·s.用这种多晶硅薄膜为有源层,所得多晶硅TFT的场效应迁移率典型值为70~80 cm~2 /V·s,亚阈值斜摆幅为1.5 V/decade,开关电流比为1.01×10~7,开启电压为-8.3 V.另外,P型的TFT在高栅偏压和热载流子偏压下具有良好的器件稳定性. 相似文献
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Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses 总被引:1,自引:0,他引:1
Min Xue Mingxiang Wang Zhen Zhu Dongli Zhang Man Wong 《Electron Devices, IEEE Transactions on》2007,54(2):225-232
Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low Vd-stress and in high Vd-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low Vd-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress 相似文献
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Aluminum was detected in the channel of a thin-film transistor after its replacement of the polycrystalline silicon source and drain junctions. The resulting transistor exhibits enhanced field-effect mobility, steeper slope of the pseudosubthreshold region, reduced turn-on voltage extrapolated from the linear regime of operation, higher on-state current, and improved immunity against short-channel effects. These improvements are consistent with a measured reduction in the density of trap states. The reduction can be attributed to the presence of aluminum in the channel 相似文献
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Cherenack K.H. Kattamis A.Z. Hekmatshoar B. Sturm J.C. Wagner S. 《Electron Device Letters, IEEE》2007,28(11):1004-1006
We have made hydrogenated amorphous-silicon thin-film transistors (TFTs) at a process temperature of 300degC on free-standing clear-plastic foil substrates. The key to the achievement of flat and smooth samples was to design the mechanical stresses in the substrate passivation and transistor layers, allowing us to obtain functional transistors over the entire active surface. Back-channel-passivated TFTs made at 300 degC on glass substrates and plastic substrates have identical electrical characteristics and gate-bias-stress stability. These results suggest that free-standing clear-plastic foil can replace display glass as a substrate from the points of process temperature, substrate and device integrity, and TFT performance and stability. 相似文献
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The dynamic negative bias temperature instability (NBTI) on low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated in detail. Experimental results revealed the threshold voltage shift of LTPS TFTs after the NBTI stress decreases with increasing frequency, which is different from the frequency-independence of conventional CMOSFET. Under a low frequency stress, the capacitance-voltage measurement with various frequencies implied that a larger quantity of inversion holes was trapped in the grain boundary. Thus, the difference of the transit time between the grain boundary and interface dominates the LTPS TFTs dynamic NBTI behaviors and results in the dependence of frequency. 相似文献
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