X波段GaN五位数字移相器MMIC的设计

采用0.5μm GaN HEMT工艺设计了X波段五位数字移相器的单片微波集成电路(MMIC),描述了移相器的设计过程,并进行了版图电磁仿真。该移相器采用高低通滤波器型网络和加载线型结构。利用电路匹配技术设计移相器电路的开关结构,将GaN器件的插入损耗从14 dB降至1 dB。版图仿真结果表明,在9.2 GHz~10.2 GHz频带范围内,均方根移相误差小于3.5°,插入损耗典型值为17.4 dB,回波损耗小于-12 dB,版图尺寸为5.0 mm×4.7 mm。     

LTCC基开关驱动低噪放一体化模块设计

基于LTCC技术设计了一款双通道应用的开关、驱动和低噪放一体化模块,利用HFSS对无源器件电感进行仿真,将电感嵌入LTCC基板中,不仅提高了模块的集成度,同时也降低了成本。在1.8~2.1 GHz频段内,ANT-RX通道增益达到23.8 dB,输入驻波比小于1.49,输出驻波比小于1.33,通道隔离大于44 dB,噪声系数小于1.21 dB(含评估板单端损耗约为0.15 dB);ANT-TX通道插入损耗小于0.42 dB(含评估版损耗约0.3 dB),输入输出驻波比均小于1.1。     

基于ADS仿真的宽带低噪声放大器设计

设计了一个S频段宽带低噪声放大器.该放大器采用两级E-PHEMT晶体管(ATF541M4)级联结构,单电源供电模式.应用微波仿真软件ADS对匹配电路进行了优化设计,最后通过S参数及谐波平衡仿真得到放大器的各项性能参数,在2.7～3.1 GHz频率范围内噪声系数小于0.6 dB,带内增益大于30 dB,带内平坦度小于±1 dB,输入输出驻波比小于1.6 dB,1 dB增益压缩点输入功率不小于-15 dBm.仿真结果表明,该设计完全满足性能指标要求.     

一种基于LTCC 技术的新型宽带增益均衡器设计

本文采用LTCC 技术设计了一种新型枝节型均衡器,将谐振单元放置在LTCC 基片的中间层,与主传输线相平行。此设计与传统均衡器相比,大大减小了均衡器体积,特别是在频段较低的均衡器设计中,这种体积的减小尤其明显。通过HFSS 仿真优化,使得该均衡器在6-18GHz 的工作频带内,低端插入损耗小于2.5dB,高端插入损耗小于1.6dB, 均衡量约10dB,输入输出回波损耗优于-16dB。     

基于ADS与HFSS的带状线功分器的设计与实现

阐述了一种新颖的仿真方法用于设计带状线功分器,该方法将ADS与HFSS联合使用,并以一款带状线功分器的设计为例,在较短时间成功制备出工作频率700~2 700 MHz,回波损耗小于-22 dB,插入损耗为3.1 dB(含分配比),带内波动小于0.1 dB,隔离度大于20 dB的高质量带状线功分器。通过比较仿真和测试结果,两者基本一致,这表明该仿真方法可大大提高仿真效率,缩短研发周期。     

基于反馈技术的宽带低噪声放大器的设计

介绍了宽带放大器的设计方法和负反馈技术。选用增益高、噪声小的高电子迁移率晶体管（HEMT）ATF54143,利用负反馈和宽带匹配技术,设计制作了一个高增益低噪声放大器,并借助于安捷伦公司的微波电路仿真软件ADS进行仿真和优化。测试表明,在50-300 MHz的频率范围内,低噪声放大器的增益大于22 dB,平坦度小于±0.3 dB,噪声系数小于1.25,输入驻波小于1.4,输出驻波小于1.3。     

微波窄带带通滤波器的设计

分析了微带线窄带滤波器设计的基本理论,借助AgilentADS仿真软件完成了中心频率位于L波段的窄带带通滤波器的设计。该滤波器选用切比雪夫的原型结构,并由耦合微带线构成,其通带为1．9GHz～2．1GHz,通带内衰减小于1．5dB,起伏小于0．5dB,在1．7GHz和2．3GHz衰减大于20dB,端口反射系数小于-15dB。版图仿真结果满足滤波器设计要求。     

基于毛纽扣的垂直互连技术研究

基于毛纽扣独特的特性,对垂直互连技术展开研究,设计了一种基于毛纽扣的垂直互连结构,通过对毛纽扣绕制成型工艺的研究,完成毛纽扣垂直互连样品的制作,并对设计的三线型毛纽扣垂直互联结构模型进行三维仿真优化和分析.通过对比分析样品测试结果与仿真结果,在测试K波段内测得插入损耗小于-0.92 dB,反射系数小于-25 dB,表明...     

基于LTCC技术的S波段双工器的设计

借助低温陶瓷共烧(LTCC)技术和三维叠层结构的设计方法,设计了有限传输零点的带通滤波器(BPF),然后通过匹配网络设计了一种S波段双工器,利用HFSS仿真软件对其对其参数进行了仿真优化。该双工器尺寸为18.4mm×15.8mm×0.6mm,在2.06GHz和2.21GHz处的插损小于-3.72dB,在1.87GHz和2.32GHz处衰减大于-55dB,在1.51GHz到2.52GHz处隔离度小于-12dB,达到了双工器设计指标要求和小型化的目的。     

一种超宽带耦合带线3dB耦合器设计

本文介绍了一种超宽带耦合带线3dB耦合器的设计.通过10%的加工公差仿真设计表明该种耦合器具有优良的性能.实际的设计结果在1.2～4.2GHz频带内插入损耗小于0.5dB,带内波纹大于-0.25dB小于 0.35dB,端口隔离大于17dB,端口驻波小于1.3.文章还对该种耦合器的峰值功率容量进行了分析,为其高功率应用提供了依据.     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

DC-20 GHz CMOS LNA using novel multilayered transmission lines and inductors

A distributed low-noise amplifier (LNA) employing novel multilayered transmission lines and inductors is designed in a standard 0.18 mum CMOS process. The new LNA provides significant improvement in performance and size with less than 13 dB return loss from DC to 17 GHz, average gain of 8plusmn0.2 dB from DC to 20 GHz, noise figure of 3.4-5 dB from 0.5-19 GHz, power consumption of 34.2 mW, and 1.05times0.37 mm ² chip size including RF pads     

LNA with wide range of gain control and wideband interference rejection

This work presents a low-noise amplifier (LNA) design with a wide-range gain control characteristic that integrates adjustable current distribution and output impedance techniques. For a given gain characteristic, the proposed LNA provides better wideband interference rejection performance than conventional LNA. Moreover, the proposed LNA also has a wider gain control range than conventional LNA. Therefore, it is suitable for satellite communications systems. The simulation results demonstrate that the voltage gain control range is between 14.5 and 34.2 dB for such applications (2600 MHz); the input reflection coefficient is less than ?18.9 dB; the noise figure (NF) is 1.25 dB; and the third-order intercept point (IIP3) is 4.52 dBm. The proposed LNA consumes 23.85–28.17 mW at a supply voltage of 1.8 V. It is implemented by using TSMC 0.18-um RF CMOS process technology.     

X波段低噪声放大器的设计

为了实现X波段的低噪声放大器,介绍了按最小噪声系数设计,采用两级级联,利用Eudyna公司的HEMT晶体管设计制作的低噪声放大器。通过专用微波电路设计软件(AWR),对该电路的稳定系数、功率增益、噪声系数、驻波比、匹配网络等进行了仿真分析。根据分析结果制作的X波段LNA取得了如下指标:在9.5～10.5 GHz频带内,功率增益大于22 dB,噪声系数小于1.5 dB,输入输出驻波小于1.7。     

0.6V CMOS低噪声放大器的设计与优化*

采用SMIC 0.18 μm CMOS工艺设计了一个低电压低功耗的低噪声放大器(Locked Nucleic Acid,LNA).分析了在低电压条件下LNA的线性度提高及噪声优化技术.使用Cadence SpectreRF仿真表明,在2.4 GHz的工作频率下,功率增益为19.65 dB,输入回波损耗S11为-12.18 dB,噪声系数NF为1.2 dB,1 dB压缩点为-17.99 dBm,在0.6V的供电电压下,电路的静态功耗为2.7 mW,表明所设计的LNA在低电压低功耗的条件下具有良好的综合性能.     

一种采用有源电感的可调增益小面积超宽带低噪声放大器

设计了一款采用可调谐有源电感（TAI）的可调增益的小面积超宽带低噪声放大器(LNA),输入级采用共基极结构,输出级采用射随器结构,分别实现了宽带输入和输出匹配;放大级采用带有反馈电阻的共射共基结构以取得宽的带宽,并采用TAI作负载,通过调节TAI的多个外部偏压使LNA的增益可调。结果表明,该LNA在2~9GHz的频带内,通过组合调节有源电感调节端口的偏压可实现S21在16.5~21.1dB的连续可调;S11小于-14.7dB;S22小于-19.3dB;NF小于4.9dB;芯片面积仅为0.049mm2。     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

A Compact Wideband CMOS Low-Noise Amplifier Using Shunt Resistive-Feedback and Series Inductive-Peaking Techniques

A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW^-1 /mm² ) which is the best results among all previous reported CMOS-based wideband LNA.     

GaAs 0.5 dB NF dual-loop negative-feedback broadband low-noise amplifier IC

A GaAs dual-loop negative-feedback low-noise amplifier (LNA) designed for the square kilometre array is presented. Effects of transformer non-idealities on LNA performance are discussed. The LNA has 0.5 dB noise figure and -10 dB input return loss from 0.6 to 1.6 GHz.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.