Activation energy of source-drain current in hydrogenated andunhydrogenated polysilicon thin-film transistors

The activation energy of the drain current in polysilicon thin-film transistors (TFTs) and the effects of hydrogenation on this energy are discussed. The activation energy data are fitted using different models of the density of states in the material. It is shown that a model which assumes a distribution of brand tail states and localized deep states can account for the activation energy data of unhydrogenated polysilicon TFTs. However, the activation energy data on hydrogenated TFTs cannot be explained with the band tail model. Instead, a simple model of deep states localized at the grain boundary can fit this data quite accurately. Also, it is shown that there is a characteristic kink in the activation energy data of the hydrogenated TFTs which is a signature of the location of the deep states relative to the valence band edge. Analysis indicates that these deep states are located approximately 0.36 eV from the valence band edge. This value is consistent with that obtained from absorption measurements using photothermal deflection spectroscopy     

Dimensional effects on the reliability of polycrystalline silicon thin-film transistors

We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I_min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated Si-H bonds.     

Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors

This letter investigates the influences of grain boundaries in the drain junction on the performance and reliability of laser-crystalized poly-Si thin film transistors (TFTs). A unique test structure where the channel region includes 150-nm-thick laser-crystalized poly-Si with small grain sizes and a 100-nm-thick one with large grain sizes is fabricated. Different behaviors in the electrical characteristics and reliability of a single TFT are observed, first under measurements of the forward mode and then under measurements of the reverse mode. This is due to the different number of grain boundaries in the drain junction. Grain boundaries in the drain junction were found to cause reduced ON/OFF current ratio, variations in threshold voltage with drain bias, significantly increased kink effect in the output characteristics, and poor hot-carrier stress endurance.     

多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管 ( poly- Si TFT) .该 poly- Si TFT由一超薄的沟道区和厚的源漏区组成 .超薄沟道区可有效降低沟道内陷阱密度 ,而厚源漏区能保证良好的源漏接触和低的寄生电阻 .沟道区和源漏区通过一低掺杂的交叠区相连接 .该交叠区使得在较高偏置时 ,靠近漏端的沟道区电力线能充分发散 ,导致电场峰值显著降低 .模拟结果显示该TFT漏电场峰值仅是常规 TFT的一半 .实验结果表明该 TFT能获得好的电流饱和特性和高的击穿电压 .而且 ,与常规器件相比 ,该 TFT的通态电流增加了两倍 ,而最小关态电流减少了3.5倍 .     

简化的非晶硅薄膜晶体管模型

本文基于两点基本假设,提出了一个简化的非晶硅薄膜场效应晶体管模型,在整个电压范围内,得到了电流的解析表达式.与现有的实验结果进行拟合,理论值与实验值符合良好.本文还分析了非晶硅薄膜晶体管输出特性中源漏串联电阻效应,结果表明,源漏串联电阻受栅压调制,近似与栅压的平方成反比.本文还解释了开启电压随温度线性变化规律.模型可用于优化非晶硅薄膜晶体管的设计.     

Unusually abrupt switching in submicrometer thin-film transistorsusing a polysilicon film with enhanced grain size

Unusually abrupt drain current change observed in polysilicon thin-film transistors (TFTs) with a channel length and width of 1 μm or smaller is discussed. The polysilicon used to fabricate the devices was deposited by low-pressure chemical vapor deposition (LPCVD) and the grain size of the film was enhanced by silicon ion implantation followed by a low-temperature anneal. The TFTs exhibited an abrupt drain current change of more than five orders of magnitude for a corresponding gate voltage change of less than 40 mV. A self-limiting positive feedback loop due to impact ionization currents and/or a parasitic bipolar effect are suggested as possible explanations     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Improvement of the reliability of amorphous silicon transistors byconduction-band tail width reduction

We present theoretical and experimental evidence showing that bias induced threshold voltage degradation of a-Si:H transistors is reduced by decreasing the width of the conduction-band tail. We show that transistors which are made using a thick (0.5 μm) a-Si:H layer possess a narrower conduction-band tail compared to transistors made using thin (0.05 μm) a-Si:H layers. We find that bias-induced threshold voltage degradation decreases by a factor of two for thick-layered TFTs compared with conventional, thin-layered TFTs. Finally, we present device design guidelines for improving the reliability of a-Si:H TFTs including several possible device designs for achieving further improvements in the reliability of a-Si:H TFTs     

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm²/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.     

Channel length influenced contribution of hole and electron trapping effect to threshold voltage stability in organic field effect transistors

Effect of channel length on hysteresis and threshold voltage shift in copper phthalocyanine (CuPc) based organic field effect transistors was studied. Contrary to expectation, longer channel length devices exhibited minimum threshold voltage shift. Influence of channel length on the contribution of hole and electron trapping to threshold voltage stability was determined. Shortest channel length devices exhibited highest electron trapping effect while longest channel devices exhibited minimum hole as well as electron trapping. Lower hole trap effect for longer channel length devices was suggested to be due to reduced longitudinal field between source and drain electrodes while minimum electron trapping was attributed to suppression of drain current by increased hole trap centres.     

New selfalignment processes for amorphous silicon thin film transistors with polysilicon source and drain

New fabrication processes for selfaligned amorphous silicon TFTs are proposed. The TFTs have a polysilicon source and drain which are formed by ArF excimer laser annealing. They exhibit a field-effect mobility of 0.8 cm/sup 2//Vs, threshold voltage of 11 V, and on/off current ratio of higher than 10/sup 6/.<>     

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.     

Novel polycrystalline silicon thin film transistors prepared by deposition from Si2H6 and subsequent annealing by NH3 plasma

This work investigated the channel layer of polycrystalline silicon (poly-Si) thin film transistors (TFTs) prepared by amorphous silicon (a-Si) films deposited using Si₂H₆ gas. The recrystallization of channel layers, source/drain, gate electrodes and post implant anneal were performed at the same time. Due to the larger grain size, the device has higher field effect mobility than SiH₄ deposited devices. These devices were also subsequently passivated by NH₃ plasma. The NH₃ plasma significantly improves the n-channel devices; however, the improvement of p-channel devices is limited. Especially, the threshold voltage of n-channel devices is significantly shifted toward the negative gate voltage than the shift magnitude of p-channel devices. To investigate the band gap width and Fermi level by determining the leakage activation energy, it is found that the channel film is changed slightly from p-type to n-type. These results may be attributed to the donor effect by NH₃ plasma passivation.     

基于高迁移率微晶硅的薄膜晶体管

近年来,微晶硅(μc-Si:H)被认为是一种制作 TFT 的有前景的材料.采用PECVD法,在低于200℃时制作了微晶硅TFTs,其制作条件类似于非晶态 TFTs.微晶硅 TFTs 器件的迁移率超过了 30 cm2/Vs,而阈值电压是 2.5 V.在长沟道器件(50～200 μm)中观测到了这种高迁移率.但对于短沟道器件(2 μm),迁移率就降低到了7 cm2/Vs.此外,该 TFTs 的阈值电压随着沟道长度的减少而增大.文章采用了一种简单模型解释了迁移率、阈值电压随着沟道长度的缩短而分别减少、增加的原因在于源漏接触电阻的影响.     

Three-dimensional analytical subthreshold models for bulk MOSFETs

Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate     

Passivation kinetics of two types of defects in polysilicon TFT byplasma hydrogenation

The effects and kinetics of hydrogen passivation on polycrystalline-silicon thin-film transistors (poly-TFTs) are investigated. Based on the response of device parameters with the progress of hydrogenation, two types of defects can be distinguished from the difference in passivation rate. The threshold voltage and subthreshold slope, which are strongly influenced by the density of dangling bond midgap states, have a faster response to hydrogenation. The off-state leakage current and field-effect mobility, related to stain-bond tail states, respond more slowly to hydrogenation, with an onset period of ~4 to 12 h depending on the grain size. Since the larger-grain-size samples showed a longer onset period, the contribution of intragranular defects to the strain-bond tail states appears to be significant     

基于陷落电荷效应的非晶硅TFT的开态电流模型

对非晶硅薄膜晶体管,提出基于陷落电荷和自由电荷分析的新方法。考虑到带隙中指数分布的深能态和带尾态,给出了基于阈值电压的开启区电流模型。定义阈值电压为栅氧/半导体界面处陷落于深能级陷阱态的电荷与陷落于带尾态的电荷相等时所对应的栅压。电流模型中,引入一陷落电荷参数β,此参数建立了电子的带迁移率与有效迁移率之间的关系。最后,将电流模型同时与Pao-Sah模型和实验数据进行比较和验证,结果表现出很好的一致性。     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

The Effects of Drain-Bias on the Threshold Voltage Instability in Organic TFTs

In this letter, the influence of drain bias on the threshold voltage instability in pentacene-based organic thin-film transistors (OTFTs) was studied. By applying different drain biases to adjust the channel carrier concentration in linear mode, the threshold voltage shift was found to be proportional to the carrier concentration. The experimental data can be well quantitatively explained by the drain bias-stress theory developed for a-Si TFTs. The outcome gives the insight of the degradation mechanism of OTFTs and is important for the design of OTFT pixel circuit, OTFT analog amplifiers, or OTFT active loads.     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶