High Aspect-Ratio Coplanar Waveguide Wideband Bandpass Filter With Compact Unit Cells

This paper introduces a micromachined thick single-metal-layer high aspect-ratio coplanar waveguide (CPW) wideband bandpass filter with compact unit cells based on the electromagnetic bandgap (EBG) concept. The filter is miniaturized as a result of using the EBG concept in design, and also by realizing high aspect-ratio structures with polymer-based deep X-ray lithography fabrication. Cascaded unit cells in the EBG model consist of capacitive and inductive parallel periodically loaded transmission lines, which determine the filter bandwidth. Compact unit cells are realized by using high aspect-ratio CPW stepped-impedance resonators. The main advantage of this approach is that the high aspect-ratio CPW structures make short unit cells practically realizable, resulting in a compact filter structure. A bandpass filter with 47% bandwidth is designed and fabricated using deep X-ray lithography, and the performance and physical size is compared to a conventional quarter-wavelength-based admittance inverter filter.      

Low-loss CPW on low-resistivity Si substrates with a micromachinedpolyimide interface layer for RFIC interconnects

The measured and calculated propagation constant of coplanar waveguide (CPW) on low-resistivity silicon (1 Ω·cm) with a micromachined polyimide interface layer is presented in this paper. With this new structure, the attenuation (decibels per centimeter) of narrow CPW lines on low-resistivity silicon is comparable to the attenuation of narrow CPW lines on high-resistivity silicon. To achieve these results, a 20-μm-thick polyimide interface layer is used between the CPW and the Si substrate with the polyimide etched from the CPW slots. Only a single thin-film metal layer is used in this paper, but the technology supports multiple thick metal layers that will further lower the attenuation. These new micromachined CPW lines have a measured effective permittivity of 1.3. Design rules are presented from measured characteristics and finite-element method analysis to estimate the required polyimide thickness for a given CPW geometry     

Si/SiO_2系统电荷对高阻硅基CPW传输损耗的影响

通过高频C-V测试得到实验制备的共平面波导(CPW)下方的Si/SiO2系统电荷主要表现为正电荷,其密度约为4.8×1010/cm2。三种不同衬底上50Ω共平面波导分别为直接制备于高阻硅上、高阻硅氧化层上、去除信号线与地线间的高阻硅氧化层上。20GHz时,测得上述三种CPW的微波传输损耗分别为-0.88dB、-2.50dB及-1.06dB,因此去除线间氧化层使得传输线损耗降低了1.44dB。此外还测试了高阻硅氧化层和除去线间氧化层的高阻硅氧化层上的两种CPW的传输损耗随外加偏压的变化。     

Conductor-loss limited stripline resonator and filters

We report on stripline resonators on thin dielectric membranes that show dispersion-free, conductor-loss limited performance at 13.5 GHz, 27.3 GHz, and 39.6 GHz. The unloaded-Q (Q_u) of the resonators increases as √f with frequency and is measured to be 386 at 27 GHz. The measured results agree well with a new conformal mapping analysis. The stripline resonators are used in a micromachined state-of-the-art planar interdigitated bandpass filter at K-band frequencies. Excellent agreement has been achieved between the microwave model at 850 MHz and the 20 GHz filter. The micromachined filter exhibits a passband return loss better than -15 dB and a conductor-loss limited 1.7 dB port-to-port insertion loss (including input/output CPW line loss) at 20.3 GHz     

Development of RF/microwave on-chip inductors using an organic micromachining process

The design and development of a micromachined spiral inductor using an organic micromachining process are presented. The process utilizes an ultra-thick negative photoresist SU-8 to elevate an inductor structure above a substrate. The micromachined inductors have been designed and fabricated on solid and hollow ground planes to, investigate the feasibility for achieving high Q-factors. The experimental results demonstrate that a micromachined inductor integrated on a Si substrate achieves a Q-factor of 19.3 at 2.1 GHz.     

Fabrication of a two-step Ni stamp for blind via hole application on PWB

This study examined imprint lithography with a two-step Ni stamp to solve the laser process problems and simultaneously form a blind via and layer pattern. The Ni stamp was fabricated by electroplating on a dry-etched Si mold, made from a SOI (silicon on insulator) wafer, and pattern replication. For the pattern transfer of the Ni stamp, hot embossing was performed on SU8-coated BT and Si wafer substrates. The residual layer was of a uniform thickness with an embossed shape of acceptable squareness.     

一种新型叉指式共面波导的设计与制作

设计制作了一种新型叉指式共面波导传输线并对其性能进行了初步的研究。通过微加工技术加厚的接地线可以减少传输线平行部分之间的相互干扰,仿真和测试表明在5~20GHz范围内其回波损耗有两个极小值,极小值的位置随传输线结构参数的变化而变化。以-20dB为基准,这两个极小值附近的带宽可以达到1.95GHz,相对带宽分别可以达到23.5%和9.97%,相应的插入损耗在0.33dB/cm和0.5dB/cm左右。这种传输线有助于减小器件整体尺寸,在带通滤波器和移相器的设计方面有重要用途。     

Probe‐Based Electro‐Oxidative Lithography of OTS SAMs Deposited onto Transparent ITO Substrates

Transparent conductive oxides like indium tin oxide (ITO) play a pivotal role in a wide range of innovative applications, such as new generations of solar cells. In many of these applications the tailoring of surface properties on the nanometer scale represents a highly desirable target. The local oxidation of self‐assembled monolayers (SAMs) using a scanning probe is a promising technique to achieve surface modifications on the nanometer scale. So far, electro‐oxidative lithography of SAMs has been reported mainly on Si wafers while there are no previous reports on transparent oxides. Here, we report the oxidative lithography of n‐octadecyltrichlorosilane (OTS) SAM deposited onto an ITO layer. A local overoxidation of the substrate is observed while the simultaneously occurring monolayer oxidation is indirectly confirmed by the site‐selective deposition of silver nanoparticles onto electro‐oxidized areas. The process of lithography is compared to that on OTS‐Si substrates and its mechanism is systematically investigated by means of scanning Kelvin probe microscopy (SKPM).     

在高阻硅衬底上制备低微波损耗的共面波导

分别在普通的低阻硅衬底、带有3μm厚氧化硅介质层的低阻硅衬底和高阻硅衬底上设计并制备了微波传输共面波导.结果表明,低阻硅衬底导致过高的微波损耗从而不能使用,通过加氧化硅介质层,微波损耗可以大大减少,但是需要较厚的氧化硅厚度.直接制备在高阻硅衬底上的共面波导在所测试的26GHz的频率范围内获得低于2dB/cm的微波损耗,而且工艺十分简单.     

Design and fabrication of a new micromachined interdigital coplanar waveguide

In this paper, a new micromachined interdigital coplanar waveguide (CPW) structure has been developed and its characteristics have been studied as a function of transmission line parameters. In interdigital CPW, the ground conductor is thickened by micromachining techniques which is helpful for reducing the interference between the adjacent center conductors while microwave transmits along it. Within the frequency range from 5 to 20 GHz, the return loss of this structure has two minimal values whose positions change with the structural parameters. The relative bandwidths reached 23.5% and 9.97% at 8.3 and 16.55 GHz while the insertion losses are about 0.33 and 0.5 dB/cm, respectively. The interdigital CPW is useful for designing bandpass filter and phase shifter and minimizing the whole size of microelectromechanical system (MEMS) devices.     

Low-voltage MOBILE logic module based on Si/SiGe interbandtunnelling diodes

Si/SiGe interband tunnelling diodes have been grown by MBE on high resistivity (n^-) silicon substrates. The device enables a very low voltage, high-speed logic on a silicon substrate. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. A maximum speed index for a 60 μm² anode area device is evaluated to 2.2 ns/V resulting in a switching speed of 0.5 ns. A logic latch built of two series connected diodes (MOBILE principle) is demonstrated, showing very robust logic operation at a supply voltage as low as 0.3 V. The used technology may be employed for a co-integration with both SiGe heterostructure bipolar- and field-effect transistor technology and may contribute to future low-voltage high speed logic on Si substrates     

低阻硅衬底上形成的低损耗共平面波导传输线

在厚膜多孔硅 (PS) /氧化多孔硅 (OPS)衬底上 ,结合聚酰亚胺涂层改善表面 ,研制低损耗、高性能射频 (RF) /微波 (MW)共平面波导CPW(CoplanarWaveguide) .通过在N和P型硅上形成不同厚度PS膜 ,并对其上的CPW进行分析比较 ,厚膜PS与石英的共面波导插入损耗非常接近 ,远小于在 2 0 0 0Ω·cm高阻硅上形成的多晶硅 -氧化硅组合衬底 :在 0 33GHz范围 ,插入损耗小于 5dB/ 1.2cm ;33 4 0GHz范围 ,小于 7.5dB/ 1.2cm .     

Improvement in Performance of Carbon Nanotube Field-Effect Transistors on Patterned SiO<Subscript>2</Subscript>/Si Substrates

Horizontally aligned single-walled carbon nanotubes (SWNTs) were fabricated on patterned SiO₂/Si substrates with groove-and-terrace structures, which were obtained using electron-beam lithography and reactive ion etching. Scanning electron microscopy observation revealed that SWNTs were aligned in the direction parallel to the groove-and-terrace structures and were preferentially grown along the edges of terraces. Using aligned SWNTs as multichannels, carbon nanotube field-effect transistors (CNTFETs) were fabricated on the patterned SiO₂/Si substrates. This method will be promising to control the direction of SWNTs on SiO₂/Si substrates for fabrication of high-performance CNTFETs with high current outputs.     

White-light emitting thin-film electroluminescent device usingmicromachined structure

A white-light emitting electroluminescent (EL) device with newly developed ZnS:Pr, Ce, F phosphor layer was fabricated inside a micromachined well having four-sided Si mirrors, prepared by anisotropic wet etching of Si (100) wafer. Highly luminant EL was achieved using the Si micromirrors. Furthermore, the EL device utilizing the metallized mirrors incorporated into the glass substrates also exhibited enhanced brightness when compared to the conventional face-emitting EL device     

A new micromachined overlay CPW structure with low attenuation overwide impedance ranges and its application to low-pass filters

In this paper, a new micromachined overlay-coplanar-waveguide (OCPW) structure has been developed and its characteristics are studied in detail as a function of the line parameters. In OCPW, the edges of the center conductors are lifted by micromachining techniques and partially overlapped with the ground plane to facilitate low-impedance lines. The elevated center conductors help to reduce the conductor loss by redistributing the current over a broad area. Comparative experiments on low-loss and lossy substrates also confirm the screening effect from the substrate losses by confining the electric field in the air between the overlapped conductor plates. Compared with the coplanar-waveguide (CPW) lines, the OCPW lines show wider impedance range (25-80 Ω) and lower loss (<0.95 dB/cm at 50 GHz). The advantages of OCPW for low-Z₀ lines are utilized to realize a high-performance stepped-impedance low-pass filter at X-band. The OCPW filter shows distinct advantages over the conventional CPW filter in terms of size, loss, skirt, and stopband characteristics     

Self-Organization of Ge(Si) Nanoisland Groups on Pit-Patterned Si(100) Substrates

Semiconductors - Space-arranged arrays of pits on Si(001) substrates were prepared using electron-beam lithography and plasma chemical etching. The positions of pits were arrange to the square and...     

Orientation dependence of HgCdTe epitaxial layers grown by MOCVD on Si substrates

Orientation dependence of HgCdTe epilayers grown by MOCVD on Si substrates was studied. Substrate orientation is considered to be one of the most sensitive factors to enable hetero-epitaxial growth on silicon substrates, especially in the case of a low temperature growth process. The present work was carried out with characterized features of a low temperature process for HgCdTe growth on Si and using a thin CdTe buffer layer. The (100), (100) misoriented toward [110], (311), (211), (111), and (331) oriented Si substrates were used in the present work. The best results were obtained on (211)Si substrates with an x-ray full width at half maximum of 153 arc sec for a 5 (im thickness HgCdTe layer and 69 arc sec for a 10 um thickness layer. It was found that the effective lattice mismatch of CdTe/Si heterosystem was reduced to 0.6% (for the 611 lattice spacing of CdTe and 333 spacing of Si) in the case of (133)CdTe/(211)Si.     

Strain Reduction in Selectively Grown CdTe by MBE on Nanopatterned Silicon on Insulator (SOI) Substrates

Silicon-based substrates for the epitaxy of HgCdTe are an attractive low-cost choice for monolithic integration of infrared detectors with mature Si technology and high yield. However, progress in heteroepitaxy of CdTe/Si (for subsequent growth of HgCdTe) is limited by the high lattice and thermal mismatch, which creates strain at the heterointerface that results in a high density of dislocations. Previously we have reported on theoretical modeling of strain partitioning between CdTe and Si on nanopatterned silicon on insulator (SOI) substrates. In this paper, we present an experimental study of CdTe epitaxy on nanopatterned (SOI). SOI (100) substrates were patterned with interferometric lithography and reactive ion etching to form a two-dimensional array of silicon pillars with ～250 nm diameter and 1 μm pitch. MBE was used to grow CdTe selectively on the silicon nanopillars. Selective growth of CdTe was confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS). Coalescence of CdTe on the silicon nanoislands has been observed from the SEM characterization. Selective growth was achieved with a two-step growth process involving desorption of the nucleation layer followed by regrowth of CdTe at a rate of 0.2 Å s^?1. Strain measurements by Raman spectroscopy show a comparable Raman shift (2.7 ± 2 cm^?1 from the bulk value of 170 cm^?1) in CdTe grown on nanopatterned SOI and planar silicon (Raman shift of 4.4 ± 2 cm^?1), indicating similar strain on the nanopatterned substrates.     

微机械陀螺仪的新进展及发展趋势

微机械陀螺仪是陀螺技术和微电子机械系统(MEMS)技术结合产生的新一代惯性器件。根据其工作原理和采用材料的不同,微机械陀螺可分为硅基微机械振动陀螺(Si-MVGs)、微机械压电振动陀螺(PVGs)和悬浮转子式微机械陀螺等。该文介绍了微机械陀螺仪的主要参数指标和应用,对硅基微机械振动陀螺(Si-MVGs)、微机械压电振动陀螺(PVGs)和悬浮转子式微机械陀螺的最新研究进展作了综合性报道,讨论了微机械陀螺未来的发展趋势。     

Avoidance of stiction in the release of highly boron doped micro-actuators fabricated using BESOI substrates

This paper presents a new technique which has been successfully applied to the fabrication of micromachined components to avoid the ‘device stiction’ often encountered during the final processing steps of micro-fabrication. Based on the use of BESOI substrates, this technique involves the heavy boron doping of the final processed structure, followed by a timed wet etch which releases the micromachined device by controllably lowering the undoped Si substrate beneath it.