Transmission property of flip chip package with adhesive interconnection for RF applications

The radio frequency (RF) and high frequency performance of the flip chip interconnects with anisotropic conductive film (ACF) and non-conductive film (NCF) was investigated and compared by measuring the scattering parameters (S-parameters) of the flip chip modules. Low cost electroless-Ni immersion-Au (ENIG) plating was employed to form the bumps for the adhesive bonding. To compare the accurate intrinsic RF performance of the ACF and NCF interconnect without lossy effect of chip and substrate, a de-embedding modeling algorithm was employed. The effects of two chip materials (Si and GaAs), the height of ENIG bumps, and the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip module were also investigated. The transmission properties of the GaAs were markedly improved on those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the RF performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the capacitive component between the bump and substrate and self inductance of the conductive particle surface in the ACF interconnect.     

基于ANSYS的挠性基板叠装互联组件热分析

长期使用环境中交变温度载荷引起的结构热疲劳会显著影响挠性基板叠装互联组件的结构强度和使用寿命.以挠性基板叠装互联组件为研究对象,基于ANSYS软件参数化建模方法建立了挠性基板叠装互联组件三维有限元模型,针对互联组件六种内部芯片布局方案进行了互联结构热特性分析并进行对比.然后基于正交试验方法分析了多种影响因素对互联组件热...     

Wireless chip to chip interconnection for multichip modules using leaky wave antennas

A novel interchip communication technique for very high speed multichip modules is presented. The feasibility of using a dielectric guide leaky wave antenna integrated on a chip for transmission and reception is discussed. J-band measurements and predictions based on a model developed using the transmission line matrix (TLM) method are compared.<>     

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension.This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability.     

超大规模红外器件混成互连的新设备与新方法

介绍了红外探测器与读出电路倒装互连工艺过程,详细对比倒装焊接机FC150和FC300的主要技术参数和功能,着重讨论了FC300新增加的自适应调平系统和干涉仪系统.回顾了法国LETI实验室应用自适应调平系统进行的2K×2K超大规模红外器件混成实验和干涉仪系统在超大规模红外器件倒装互连方面的应用.     

Packet-switched on-chip interconnection network for system-on-chip applications

Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network to overcome limitations of bus architecture. In this brief, we propose a packet-switched on-chip interconnection network architecture, through which multiple processing units of different clock frequencies can communicate with each other without global synchronization. The architecture is analyzed in terms of area and energy consumption, and implementation issues on building blocks are addressed for cost-effective design. A test chip is implemented using 0.38-/spl mu/m CMOS technology, and measured its operation at 800 MHz to demonstrate its feasibility.     

垂直腔面发射激光器及其进展

1　引　　言　　光电子技术在网络、存储器等方面的应用与多媒体信息社会的发展息息相关 ,对信息社会的发展始终起着至关重要的作用。在世界范围内的信息基础设施配置中 ,人们对以光纤通信为代表的光电子技术寄予厚望。瞬间传送处理图像等大规模信息技术愈益重要 ,在并行传递空间信息的超并行光传输系统、连接多台计算机或LSI芯片的并行光互连及光并行信息处理系统中 ,新兴的并行光电子技术起主导作用。要实现充分利用光的并行性的系统 ,大规模地进行二维集成化的并行光器件十分重要。为适应这种需求 ,人们开始探索一种新型结构的半导体激…     

The effect of reflow process on the contact resistance and reliability of anisotropic conductive film interconnection for flip chip on flex applications

The work presented in this paper focuses on the effect of reflow process on the contact resistance and reliability of anisotropic conductive film (ACF) interconnection. The contact resistance of ACF interconnection increases after reflow process due to the decrease in contact area of the conducting particles between the mating I/O pads. However, the relationship between the contact resistance and bonding parameters of the ACF interconnection with reflow treatment follows the similar trend to that of the as-bonded (i.e. without reflow) ACF interconnection. The contact resistance increases as the peak temperature of reflow profile increases. Nearly 40% of the joints were found to be open after reflow with 260 °C peak temperature. During the reflow process, the entrapped (between the chip and substrate) adhesive matrix tries to expand much more than the tiny conductive particles because of the higher coefficient of thermal expansion, the induced thermal stress will try to lift the bump from the pad and decrease the contact area of the conductive path and eventually, leading to a complete loss of electrical contact. In addition, the environmental effect on contact resistance such as high temperature/humidity aging test was also investigated. Compared with the ACF interconnections with Ni/Au bump, higher thermal stress in the Z-direction is accumulated in the ACF interconnections with Au bump during the reflow process owing to the higher bump height, thus greater loss of contact area between the particles and I/O pads leads to an increase of contact resistance and poorer reliability after reflow.     

导电胶在倒装芯片互连结构中的应用进展

介绍了导电胶的基本分类以及导电胶的渗透理论;讨论了各向异性导电胶(ACA)、各向同性导电胶(ICA)、绝缘粘合剂(NCA)在倒装芯片互连结构中的应用;分析了导电胶互连的可靠性。最后展望了导电胶的发展趋势。     

芯片内/间无线互连技术发展综述

为了解决超大规模集成电路布线复杂的问题,无线互连技术(WIT)应运而生。介绍了实现芯片内/间无线互连的两类技术,一类是基于片上天线的无线互连技术,另一类是基于AC耦合的无线互连技术。从实现成本、功耗,传输性能方面对这两类技术进行了分析与比较,讨论了它们的具体应用及适用范围,同时也总结了两者目前存在的问题,并指出了其未来的研究方向,对今后芯片内/间无线互连技术的应用研究具有一定的参考意义。     

Hybrid integration technology of planar circuits and NRD-guide forcost-effective microwave and millimeter-wave applications

An architecture called the hybrid planar/non-radiative-dielectric (NRD) waveguide integrated technology is proposed as a building block for constructing microwave and millimeter-wave circuits. This hybrid approach of integration offers a unique possibility of exploiting inherent complementary advantages of planar structures and NRD waveguides for low-cost wireless applications while eliminating the potential drawbacks associated with both dissimilar structures. Compared to the existing NRD-guide related technology, the proposed framework consists of relocated planar structures on the top and/or the bottom plates of an NRD-guide, sharing the common ground planes. Such a hybrid scheme is particularly suitable for millimeter-wave systems in which active devices can be made with the planar-line technique while passive components can be made with the NRD-guide technique. The two subsets of a complete functional system are interconnected through a class of aperture-based transitions which can be designed to have wide-band performance. In addition, the multichip module (MCM) technique is readily achieved under this proposed scheme. Experimental prototypes, including passive-component and active-device, based on the new hybrid technology presented in this paper, show that the novel hybrid technology promises to be useful in the design of future microwave and millimeter-wave circuits and systems     

外腔面发射激光器GaAs基质的酸性腐蚀

外腔面发射激光器的GaAs基质厚度大,热导率低,严重阻碍有源区热量的扩散,影响激光器功率的提高。为了去除激光器的GaAs基质,采用硫酸系酸性腐蚀,通过改变腐蚀液浓度和腐蚀温度来比较腐蚀液对GaAs基质的腐蚀影响,并采用原子力显微镜照片表征了腐蚀表面的粗糙度。结果表明,当腐蚀液的体积比V（H2SO4）:V（H2O2）:V（H2O）=1:5:10,腐蚀温度为30℃时,腐蚀速率适中,为5.2μm/min,腐蚀表面粗糙度2.7nm,腐蚀总体效果较为理想。较好的GaAs基质腐蚀效果为外腔面发射激光器衬底去除腐蚀阻挡层的选择性腐蚀提供了基本的保障。     

Optoelectronic multichip module integration for chip level opticalinterconnects

We have integrated an 850-nm vertical-cavity surface-emitting laser (VCSEL), its driver, and a diffractive lenslet array onto a single substrate to produce an integrated optoelectronic multichip module for signal fan-out and distribution. The diffractive element performs optical fan-out of the output beam from the VCSEL into an array of focused spots at a plane 1, 416 μm from the surface of the VCSEL. This corresponds to 160 μm from the surface of the diffractive lens. System design, fabrication, integration, and experimental characterization is presented     

多链接透明互联技术及应用

传统的IEEE 802.1局域网使用STP构建层次化的无环路的网络,但是随着网络规模的扩大和网络内部横向流量的增多,这种模型逐渐不适应大范围二层网络的接入和扩展。文中介绍了一种IETF工作组定义的新技术———TRILL,在现有的IEEE 802.1框架内,将网络层的路由协议应用到链路层,实现数据最短路径和多路径的转发,满足了大规模园区网络和数据中心的建设。     

Monolithic integration of vertical-cavity surface-emitting laserand diffractive optical element for advanced beam shaping

We have demonstrated a vertical-cavity surface-emitting laser (VCSEL) with a monolithically integrated diffractive optical element (DOE) for advanced beam shaping. The DOE is a two-level surface relief, etched into the GaAs substrate beneath a bottom-emitting VCSEL. The combination generates a 4×4 array of focused spots 10 mm from the substrate with spot sizes down to less than 400 μm, almost at the diffraction limit. Diffraction efficiencies of 29% and uniformity errors of 14% were measured     

Monolithic integration of continuous-relief diffractive structures with vertical-cavity surface-emitting lasers

In this work, we have studied the transfer of diffractive optical elements (DOEs), originally made in resist, into GaAs for monolithic integration with vertical-cavity surface-emitting lasers (VCSELs). The DOEs are blazed gratings and Fresnel lenses, and have been fabricated on the back surface of bottom emitting VCSELs using electron-beam lithography or replication by hot embossing in resist followed by a quick-dry etch step. Diffraction efficiency was measured to be 81% in the first order of diffraction for the blazed grating.     

Modified helix chip antenna for WiBro and WLAN applications

A modified helix chip antenna is presented for WiBro and WLAN applications. The impedance and radiation characteristics of the antenna are investigated. The antenna is formed on both sides of the substrate (3.5 times 8 times 0.8 mm, FR4). The measured results show that the proposed antenna has a bandwidth of 290 MHz (2.26-2.55 GHz) and a maximum radiation gain of 1.468 dBi.     

Method for modelling substrate coupling in large chip designs

The authors present a novel method for modelling substrate noise in large mixed-signal SPICE designs. The approach is very efficient and can be applied to large designs with many digital blocks. An example circuit, which cannot be efficiently analysed with any current method, is used to demonstrate this new method