Temperature scaling for 35 nm gate length high-performance CMOS

It is commonly assumed that reducing the source–drain extension (SDE) junction depth is a key element for next-generation technology nodes. This can either be achieved by reducing the implantation energy or by reducing the thermal budget of the annealing process.In this paper, we will demonstrate that for transistors with an optimum balance between AC and DC performance a reduction in junction depth results only in very little improvement of the short-channel behaviour for spike anneals in the temperature range between 1050 and 1130 °C. On the other hand, reduced temperatures allow a reduction in in-die parameter variation and therefore improved product performance. There exists an optimum temperature which represents a compromise between reduced parameter variation and reduced dopant activation.For improved threshold voltage roll-off we introduced heavily doped low-energy halos, thus obtaining a physical gate length of 35 nm. The problem of increased drain resistance due to reduced activation at lower temperatures and counter-doping with high halo implant doses was solved by optimizing the lateral diffusion of the deep source–drain regions.All electrical data have been extracted from our triple-spacer transistor architecture, manufactured in 90-nm production technology. An outlook will be given for alternative device concepts, such as SPE and Laser anneal and asymmetric devices.     

Scaled GaAs MESFET's with gate length down to 100 nm

Fully ion-implanted GaAs depletion MESFET's with gate lengths from 1 µm down to 0.1 µm and with closely spaced source and drain contacts have been fabricated with electron-beam lithography. Gate-length dependence of transconductance, capacitance, output conductance, and threshold voltage is presented. Maximum transconductance obtained was 370 mS/mm for 0.1-µm gate length. The experimental data indicate that shallow implants do indeed result in better devices, but further vertical scaling of the devices is mandatory.     

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.     

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.     

A new approach to simulating n-MOSFET gate current degradation byincluding hot-electron induced oxide damage

A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N_it ) and oxide trapped charge (Q_ox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N_it and Q_ox has thus been proposed. Furthermore, the individual contributions of N_it and Q_ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I_G,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices     

A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide,shallow implanted source and drain and BF2 pockets

We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick. We have achieved devices with real N^- arsenic implanted extensions and BF₂ pockets. The devices operate reasonably well down to 20-nm physical gate length. These devices are the shortest devices ever reported using a conventional architecture     

65nm n沟MOSFET的重离子辐照径迹效应研究

重离子在SiO2中能产生永久径迹,因此它可能对MOS器件电学特性产生影响。文章用Geant4软件对Au和Sn两种离子进行蒙特卡洛模拟,重点分析高能粒子在SiO2中的能量沉积及径迹。基于模拟分析,对专门设计的65 nm n沟MOSFET器件进行Sn离子辐照实验,发现辐照后Ids和Ig明显增大,分析器件辐照前后阈值电压、跨导、沟道电流以及栅漏电流等特性参数变化的原因。     

Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing

The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The MOSFET performance can be improved and its deviation suppressed by using FLA. In analyzing MOSFETs with gate length (L) of 20 nm by computer simulations, it was clarified that in contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |I/sub off/| with a low channel surface dopant concentration. This provided a higher mobility value and a higher drive current. FLA is promising for improving the performance and productivity of sub-30-nm gate-length MOSFETs.     

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

A comparative study of gate direct tunneling and drain leakagecurrents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents     

40nm 3G TD-SCDMA

展讯通信有限公司(Spreadtrum Communications,Inc.)与TSMC共同宣布其全球首款40纳米TD-SCDMA商用基带处理器这一合作成果。通过优化设计、工艺和生产方式,双方实现了该基带处理器一次性流片成功的佳绩。目前TSMC位于台湾的超大型晶圆厂(GIGAFAB)之一的晶圆十二厂已经开始生产该芯片。     

40 nm 3 G TD-SCDMA

展讯通信有限公司（Spreadtrum Communications,Inc．）与TSMC共同宣布其全球首款40纳米TD—SCDMA商用基带处理器这一合作成果。通过优化设计、工艺和生产方式,双方实现了该基带处理器一次性流片成功的佳绩。目前TSMC位于台湾的超大型晶圆厂（GIGAFAB）之一的晶圆十二厂已经开始生产该芯片。     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8-μm gate length, and measures 6.3 mm×4.8 mm. A basic gate delay of 40 ps has been achieved. A 16×16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W     

采用环栅和C-Element技术相结合的方法对寄存器单元进行加固

This paper presents a radiation hardened flip-flop with an annular gate and a Muller C-element. The proposed cell has multiple working modes which can be used in different situations. Each part of the cell can be verified easily and completely by using different modes. This cell has been designed under an SMIC 0.13 μm process and 3-D simulated by using Synopsys TCAD. Heavy-ion testing has been done on the cell and its counterparts. The test results demonstrate that the presented cell reduces the cell＇s saturation cross section by approximately two orders of magnitude with little penalty on performance.     

Sub-40 nm SOI V-groove n-MOSFETs

We present output and transfer characteristics of single-gated, 36 nm, 46 nm and 56 nm channel length SOI MOSFETs with a V-groove design. For the shortest devices we find transconductances as high as 900 μS/μm and drive currents of 490 μA/μm at V_gs - V _th=0.6 V. The V-groove approach combines the advantages of a controlled, extremely abrupt doping profile between the highly doped source/drain and the undoped channel region with an excellent suppression of short-channel effects. In addition, our V-groove design has the potential of synthesizing devices in the 10 nm range