CMOS single-ended-to-differential low-noise amplifier

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage.     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

CMOS毫米波低功耗超宽带共栅低噪声放大器

陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA).该LNA用标准90-nm RFCMOS工艺实现并具有如下特征:在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2dB,平均NF在27 ～ 42 GHz频段内为5.1 dB;S11在整个测试频段内小于-11 dB.40 GHz处输入三阶交调点(IIP3)的测试值为+2 dBm.整个电路的直流功耗为5.3 mW.包括焊盘在内的芯片面积为0.58 mm×0.48 mm.     

一种应用于6-9GHz UWB系统的低噪声CMOS射频前端设计

本文介绍了一种应用于6-9 GHz超宽带系统的全集成差分CMOS射频前端电路设计。在该前端电路中应用了一种电阻负反馈形式的低噪声放大器和IQ两路合并结构的增益可变的折叠式正交混频器。芯片通过TSMC 0.13µm RF CMOS工艺流片,含ESD保护电路。经测试得该前端电路大电压增益为23~26dB,小电压增益为16~19dB;大增益下前端电路平均噪声系数为3.3-4.6dB,小增益下的带内输入三阶交调量(IIP3)为-12.6dBm。在1.2V电压下,消耗的总电流约为17mA。     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

A SiGe LC-ladder low noise amplifier with base resistance match,gain and noise flatness for UWB applications

This study presents a 3.1–10.6 GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18 µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S₂₁) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33 mW power and achieves S₂₁ of 20.65+0.7 dB, NF of 2.79+0.2 dB over the band of 3.1–10.6 GHz. The simulated input third-order intermodulation point (IIP3) is −17 dBm at 10 GHz.     

Sub-mA single ended CMOS low noise amplifier with 2.41 dB noise figure

This paper presents a single ended low noise amplifier (LNA) using 0.18 μm CMOS process packed and tested on a printed circuit board. The LNA is powered at 1.0 V supply and drains 0.95 mA only. The LNA provides a forward gain of 11.91 dB with a noise figure of only 2.41 dB operating in the 0.9 GHz band. The measured value of IIP3 is 0.7 dBm and of P1dB is −12 dBm. Zhang Liang is currently with Cyrips, Singapore. Ram Singh Rana was born in Delhi (India). Having primary education in Bijepur, Dwarahat(India), he received the B.Tech. (hons.) degree in Computer Engineering from G.B. Pant University, Pantnagar, India in 1988 and the Ph.D degree from the Indian Institute of Techonology (IIT), Delhi, India in 1996. He worked for his Ph.D in the Centre for Applied Research in Electronics, IIT Delhi in close interaction with the Semiconductor Complex Limited, Mohali, India. He was with ESPL, Mohali(India) in 1988 for a very short period and then served IIT Delhi as Senior Research Associate (88-90) and Senior Scientific Officer (90-95) where his main contributions were on CMOS analog IC design in subthreshold operation. He was a Lecturer in the Kumaon Engg. College, Dwarahat (India) before serving the IIT Roorkee (Formerly Univ. of Roorkee) in 1998 as assistant Professor. In 1999, he was a Manager (Engineering), Semiconductor Product Sector of the Motorola, Noida, India. Since joining the Institute of Microelectronics, Singapore in 2000, he worked mostly on RFICs, Fractional-N PLLs, ADCs. During 2001-2004, he worked there as IC Design Research and Training Program Manager. Currently, he is serving the institute as Senior Research Engineer in CMOS IC design (below 1V) for biomedical and bio-sensors. His current interests include design and consultancy for CMOS ICs/systems for the biomedical and high speed communication applications. Dr. Rana received Young Teacher Career Award from the All India Council for Technical Education in 1997. He was an Adjunct Asstt. Professor with the National University of Singapore (NUS), Singapore in 2004. He is sole inventor of two US granted patents and has filed several other patents. He has authored/co-authored about 40 publications. He has been reviewer for several IEEE journals and conference papers. Dr Rana is a senior member of IEEE and a member of Graduate Program in BioEngineering, NUS Singapore. He has chaired /co-chaired sessions in many international conferences. Zhang Liang was born in China in June 1978. He received the Bachelor degree and the Master degree in Electrical Engineering from the Xi’an JiaoTong University, Xi’an, China, in 2000 and 2003 respectively. Since 2003, he has been a postgraduate student in the Electrical and Computer Engineering department, National University of Singapore(NUS), Singapore and has successfully completed M.Engg degree program of the NUS. He is currently working on RFICs as a design engineer in Cyrips, Singapore. His design and research interests include integrated circuit design for communications. He has authored/co-authored several publications of international standard. Hari K Garg obtained his BTech degree in EE from IITDelhi in 1981. Subsequently, he obtained his MEng & PhD degrees from Concordia University in 1983 & 1985, and MBA from Syracuse University in 1985. He was a faculty member at Syracuse University from 1985 till 1995. He has been with the National University of Singapore since 1995 till present with the exception of 1998-1999 when he was with Philips. Hari’s research interests are in the area of digital signal/image processing, wireless communications, coding theory and digital watermarking. He has published extensively on these and related topics. He is also founder of several companies in the space of mobile telephony. In his spare time, Hari enjoys singing and a good game of Squash.     

1V高线性度2.4GHz CMOS低噪声放大器

讨论了低噪声放大器(LNA)在低电压、低功耗条件下的噪声优化及线性度提高技术.使用Chartered 0.25μm RF CMOS 工艺设计一个低电压折叠式共源共栅LNA.后仿真结果表明在1V电源下,2.36GHz处的噪声系数NF仅有1.32dB,正向增益S21为14.27dB,反射参数S11、S12、S22分别为 -20.65dB、-30.27dB、-24dB,1dB压缩点为-13.0dBm,三阶交调点IIP3为-0.06dBm,消耗的电流为8.19mA.     

基于CMOS工艺的低噪声、高增益混频器

基于TSMC 0.18μm CMOS工艺,设计了一种低噪声、高增益的混频器.通过在吉尔伯特单元中的跨导级处引入噪声抵消技术以降低混频器的噪声;并且在开关管的源级增加电流注入电路的基础上并联一个电容与开关管共源节点处的寄生电容谐振,进一步降低混频器的噪声,增大电路的增益.仿真结果表明,在本振（LO）频率为2.395 GHz,射频（RF）频率为2.4GHz时,混频器的增益为14.2dB,双边带噪声系数为5.9dB,输入三阶交调点为-3.2dBm.混频器工作电压1.8V,直流电流为8mA.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

Low-power highly linear UWB CMOS mixer with simultaneous second- and third-order distortion cancellation

A 3.1-4.8 GHz mode-1 UWB CMOS mixer that utilizes simultaneous second- and third-order distortion cancellation is presented. The scheme is based on a new derivative superposition, employing PMOS as an auxiliary FET to cancel the second- and the third-order nonlinear currents of common-source transconductance in the mixer and gives rise to low-distortion operation for a broad range of gate-source voltage. Full Volterra series analysis of the proposed transconductance is reported to examine the effectiveness of the new technique. Simulations in a 0.13 μm CMOS technology demonstrate that IIP3 and IIP2 of the proposed mixer have 18 and 10 dB improvements, respectively, compared with conventional Gilbert-type mixer with the same power consumption. The robustness of the technique has been verified by Monte Carlo analysis. The mixer has a gain of 12 dB and noise figure of 13 dB, while drawing only 2.5 mA from 1.2 V supply voltage.     

CMOS混频器设计现状与进展

详细阐述了CMOS混频器设计技术的进展，着重介绍了CMOS混频器各项性能优化技术的现状与进展，探讨了各种技术的优缺点。最后，总结了CMOS混频器有关转换增益、线性度以及噪声系数的成果报道。     

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

基于噪声抵消技术的低功耗C频段差分低噪声放大器

设计了一款"基于噪声抵消技术的低功耗C频段的差分低噪声放大器。该放大器由输入级、放大级以及输出缓冲级3个模块构成,其中输入级采用电容交叉耦合的差分对与直接交叉耦合结构差分对级联,实现输入匹配及噪声抵消;放大级采用具有电阻-电感并联反馈的电流复用结构来获得高的增益、良好的增益平坦性及低的功耗;输出缓冲级采用源跟随器结构,实现良好的输出匹配。基于TSMC 0.18μm CMOS工艺库,验证表明在C频段,放大器的增益为20.4设计了一款??基于噪声抵消技术的低功耗C频段的差分低噪声放大器。该放大器由输入级、放大级以及输出缓冲级3个模块构成,其中输入级采用电容交叉耦合的差分对与直接交叉耦合结构差分对级联,实现输入匹配及噪声抵消;放大级采用具有电阻-电感并联反馈的电流复用结构来获得高的增益、良好的增益平坦性及低的功耗;输出缓冲级采用源跟随器结构,实现良好的输出匹配。基于TSMC 0.18 μm CMOS工艺库,验证表明在C频段,放大器的增益为20.4??0.5 dB,噪声系数介于2.3~2.4 dB之间,输入和输出的回波损耗均优于-11 dB,稳定因子恒大于1,在6.5 GHz下,1 dB压缩点为-16.6 dBm,IIP3为-7 dBm,在2.5 V电压下,电路功耗仅为6.75 mW。     

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...     

一种具有新型增益控制技术的CMOS宽带可变增益LNA

高速超宽带无线通信的多标准融合是未来射频器件的发展趋势,该文提出一种基于CMOS工艺、具有新型增益控制技术的宽带低噪声放大器(LNA),采用并联电阻反馈实现宽带输入匹配,并引入噪声消除技术来减小噪声以提高低噪声性能;输出带有新型6位数字可编程增益控制电路以实现可变增益。采用中芯国际0.13m RF CMOS工艺流片,芯片面积为0.76 mm2。测试结果表明LNA工作频段为1.1-1.8 GHz,最大增益为21.8 dB、最小增益8.2 dB,共7种增益模式。最小噪声系数为2.7 dB,典型的IIP3为-7 dBm。     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB (-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.