A compact broadband MMIC sub-harmonic mixer using quasi-lumped transmission lines

A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70 nm GaAs mHEMT technology is demonstrated for 60 GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5×0.77 mm². The conversion gain is optimized by a quasi-lumped 90° phase shift stub. Experimental results show that from 50 GHz to 70 GHz, the conversion gain varies between −12.1 dB and −15.2 dB with a LO power level of 10 dBm and 1 GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5 dB, 21.3 dB and 25.8 dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1 dB compression point of -2 dBm and exhibits outstanding figure-of-merits.     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.     

Nonlinear effect mitigation based on PAPR reduction using electronic pre-distortion technique in direct-detection optical OFDM system

The nonlinear effect induced by the Mach–Zehnder modulator (MZM) and optical self-phase modulation (SPM) in the presence of high peak-to-average power ratio (PAPR) is investigated theoretically. We theoretically and experimentally investigate the direct-detection optical orthogonal frequency-division multiplexing (DD-OOFDM) system with an electronic pre-distortion technique of companding transform (CT) to reduce the peak-to-average power ratio (PAPR) of OFDM signals and improve the receiver sensitivity. Experimental results show that the PAPR reduction can reach about 3 dB when the complementary cumulative distribution function is 1 × 10⁻⁴, which means the number of random OFDM signals is 1 × 10⁴, and the receiver sensitivity is improved by 0.7, 1.7, and 2.4 dB for the launch power of 2, 6 and 10 dB m, respectively, at the BER of 1 × 10⁻⁴ after transmission over 100-km single-mode fiber with the μ of 2. It shows that the PAPR reduction can mitigate not only the nonlinearity of MZM, but also the nonlinear phase noise in the fiber link when the optical power into fiber is high.     

Effect of annealing temperature on optical and electrical properties of lead sulfide thin films

Lead sulfide (PbS) thin films with 150 nm thickness were prepared onto ultra-clean quartz substrate by the RF-sputtering deposition method. Deposited thin films of PbS were annealed at different temperatures 100 °C, 150 °C, 200 °C, 250 °C and 300 °C. X-ray diffraction pattern of thin films revealed that thin films crystallized at 150 °C. Crystalline thin films had cubic phase and rock salt structure. The average crystallite size of crystalline thin films was 22 nm, 28 nm and 29 nm for 150 °C, 200 °C and 250 °C respectively. From 150 °C to 250 °C increase in annealing temperature leads to increase in crystallite arrangement. FESEM images of thin films revealed that crystallite arrangement improved by increasing annealing temperature up to 250 °C. Increase in DC electrical conductivity by increasing temperature confirmed the semiconductor nature of crystalline thin films. Increase in dark current by increasing annealing temperature showed the effect of crystallite arrangement on carrier transport. Photosensitivity decreased by increasing annealing temperature for crystalline thin films that it was explained at the base of thermal quenching of photoconductivity and adsorption of oxygen at the surface of thin films that leads to the formation of PbO at higher temperatures.     

Distributed NGD active circuit for RF-microwave communication

This paper is aimed to the investigation on innovative distributed negative group delay (DNGD) circuits for RF communication. Thanks to the analogy between the lumped and distributed circuits, NGD circuit topologies were identified. By using the S-parameter theory, analysis and synthesis methods of these topologies are proposed. The DNGD circuits developed are mainly comprised of a transistor combined with a series resistance ended by a stub. Then, synthesis relations enabling to determine the NGD circuit parameters from the desired NGD and gain values are established. As application, an active phase shifter (PS) operating independently with the frequency based on the cascade of PGD and NGD devices was synthesized. First, an NGD PS with transmission phase of (135 ± 5)° around 2.56 GHz over the bandwidth of about 1.02 GHz was obtained. Then, a two-stage DNGD PS exhibiting 90° with ±10° flatness from 4.1 GHz to 6.8 GHz was designed. The DNGD circuit presented can be used in various telecommunication areas notably for correcting RF/numerical signal delays in the RF-microwave analogue-digital devices.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

A PAPR reduction technique using Hadamard transform combined with clipping and filtering based on DCT/IDCT for IM/DD optical OFDM systems

In Intensity Modulator/Direct Detection (IM/DD) optical OFDM systems, the high peak-to-power average ratio (PAPR) will cause signal impairments through the nonlinearity of modulator and fiber. In this paper, a joint PAPR reduction technique based on Hadamard transformation and clipping and filtering using DCT/IDCT transform has been proposed for mitigating the impairments in IM/DD optical OFDM system. We then experimentally evaluated the effect of PAPR reduction on the bit error rate (BER) performance and the results show the effectiveness of the proposed technique. At a bit error rate (BER) of 1 × 10⁻³, the receiver sensitivity of the proposed 2.5 Gb/s IM/DD optical OFDM system after 100-km standard single-mode fiber transmission has been improved by 0.8 dB, 1.3 dB and 3.1 dB for a launch power of 6.4 dBm, 8 dBm and 10 dBm respectively when compared with the classical system.     

Sub-1 V,pico-watt subthreshold CMOS voltage reference circuit with dual temperature compensation

A pico-watt CMOS voltage reference is developed using an SK Hynix 0.18 µm CMOS process. The proposed architecture is resistorless and consists of MOSFET circuits operated in the subthreshold region. A dual temperature compensation technique is utilized to produce a near-zero temperature coefficient reference output voltage. Experimental results demonstrate an average reference voltage of 250.7 mV, with a temperature coefficient as low as 3.2 ppm/°C for 0 to 125 °C range, while the power consumption is 545 pW under a 420 mV power supply at 27 °C. The power supply rejection ratio and output noise without any filtering capacitor at 100 Hz are −54.5 dB and 2.88 µV/Hz^1/2, respectively. The active area of the fabricated chip is 0.00332 mm².     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Empirical prediction model for Li/SOCl2 cells based on the accelerated degradation test

The empirical prediction model of residual capacity (Cap) for D-size Li/SOCl₂ cells has been developed and validated based on the accelerated degradation test (ADT) data. In this experiment, a series of constant storage temperatures (25 °C, 55 °C, 70 °C, and 85 °C) was selected and the residual capacity of each cell was monitored continuously during the aging test. The model was established by fitting twice. Firstly, time dependence of Cap (t, T) was investigated. Secondly, the generalized model of residual capacity was built. The prediction model, as a function of storage time and temperature, can precisely predict the value of residual capacity. The generalized empirical model of Cap, involving two aging processes, is valid for the degradation condition of temperatures from 25 °C to 70 °C. The first aging process completed rapidly within 7 days. The second aging process was accelerated by temperature with time^1/2 kinetics. For the cells stored at 85 °C, another failure mechanism may exist based on the departure of linear fitting coefficients.     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

An 8 bit, 100 kS/s,switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm². The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10²⁰, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.     

Improved performance step impedance lowpass filter

Performances of the conventional Butterworth step impedance lowpass filters (LPF) are significantly improved by placing transmission zero either closer to the cut-off frequency (f_c) or away from it. It is achieved by using transverse resonance width of the capacitive line sections. We report method of designing transverse resonance type LPF (TR-LPF) for 5 to 11-pole filters. At f_c = 2.5 GHz, we obtained selectivity in the range 113.3–56.66 dB/GHz and 20–60 dB rejection BW in the range 9.61–7.29 GHz. The TR-LPF can suppress the stopband signal by 60 dB up to 5f_c. Insertion loss in passband is within 0.72 dB. Improved performance of TR-LPF can be designed for f_c up to 7.5 GHz.     

Reliability of high voltage/high power L/S-band Hbt technology

This paper presents the qualification methodology and results of an InGaP HBT process industrialised by UMS to cover high power L and S band applications. The high level of robustness of the technology has been demonstrated with RF test up to 9 dB compression without any degradation. MTTF of 12 FIT/mm² of semiconductor at a junction temperature of 175 °C have been demonstrated based on more than 560,000 component hours. Also, following the activation period, an asymptotic decrease of the Beta is pointed out both at WLR and long term reliability test and modelled by a Black law. Activation energy between 0.52 and 0.75 eV and a Black factor between 1 and 2 was found. An original and complete failure analysis methodology including NIR emission microscopy, FIB and TEM analysis, have been used to characterised infant mortality for which the root cause is attributed to the propagation through the base–emitter junction of dislocation in the epitaxy. Activation energy of 0.58 eV was determined for this mechanism.     

Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75°, 80°, 85° and 90°. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80° for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1×10¹⁵ to 5×10¹⁵ cm⁻³) cause increase of T-TSV capacitance by about 25 fF, −12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

Utility of RF MEMS miniature switched capacitors in phase shifting applications

This paper demonstrates research carried out towards the development of switched capacitors having miniature dimensions. Such devices are based on the Radio Frequency Micro Electro Mechanical Systems (RF MEMS) technique which has gained prominence in implementing a wide variety of microwave and millimetre devices till date. Switched capacitors having standard or conventional dimensions are prone to several limitations which are addressed by scaling down the standard dimensions by 150× times (in terms of area requirement). Such switched capacitors are employed to develop phase shifters working in K-band (22 GHz) frequency range to yield appreciable performance both in terms of electromechanical and RF characterizations. Such switched capacitors are utilized to develop phase shifters which find immense applications in the design of Phased Array RADARs. Switched capacitors fabricated on 500 µm thick quartz substrates, result in 30° phase shift (0.66 mm × 1 mm in dimension) with associated minimum −0.18 dB insertion loss and better than −21 dB reflection coefficient at 22 GHz frequency. Electromechanical characterization reports an actuation voltage of 14.6 V, mechanical vibration frequency of 2.5 MHz and a switching time of 620 ns respectively. Demonstrations showing complete realization of 180° phase shifter (4 mm × 1 mm) employing a cascaded arrangement of six similar 30° unit cells are also included in this paper.     

Dependence of the optoelectronic properties of selenium-hyperdoped silicon on the annealing temperature

Selenium-hyperdoped silicon was prepared by ion implantation at 100 eV to a dose of 6×10¹⁵ Se/cm², followed by furnace annealing at 500–900 °C for 30 min. A phase transition from amorphous to crystalline was observed for the sample annealed at 600 °C. Carrier density in the Se doping layer gradually increases with the annealing temperature and a high carrier/donor ratio of 7.5% was obtained at 900 °C. The effects of annealing temperature on the rectifying behavior and external quantum efficiency of n⁺p junctions formed on Se-hyperdoped silicon were also investigated. We found that 700 °C was the optimal annealing temperature for improving the crystallinity, below-bandgap absorption, junction rectification and external quantum efficiency of Se-doped samples.     

Photo stability enhancement of Poly(3-hexylthiophene)-PCBM nanocomposites by addition of multi walled carbon nanotubes under ambient conditions

Poly(3-hexylthiophene)-Phenyl-C61-butyric acid methyl ester (P3HT–PCBM) composites find wide application in optoelectronic devices, especially bulk-hetero junction (BHJ) solar cells. These composites, even though could give efficient polymer solar cells with ∼4–5% power conversion efficiencies (PCE), a major problem of photo stability is associated with it and remains unsolved. P3HT–PCBM composite was found to be degrading on irradiation with ultraviolet radiation or a solar simulator providing AM1.5G illumination (1000 W m^–2, 72 ± 2 °C or 330 W m⁻², 25 °C), in presence of oxygen and moisture. Here, we have studied the photo stability of P3HT–PCBM under ambient conditions and showed that a new ternary composite, P3HT–PCBM–MWCNT (multi walled carbon nanotube) has superior photo stability even on extended UV–Vis exposure. A total of 7% (w/w) PCBM and 3% (w/w) MWCNT with respect to P3HT resulted in optimum stability. UV–Visible and fluorescence spectral analysis have been used to study the photo stability, both in solution state and solid/film state. Transmission electron micrograph (TEM) along with selected area electron diffraction (SAED) pattern and Field Emission Scanning Electron Microscopy (FE-SEM) micrographs have been used to show the well coating of MWCNT on P3HT–PCBM composite. Since MWCNT is one of the very important carbon based nanomaterial with several supreme characteristics, this new ternary composite has great importance for optoelectronic applications.     

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 µm TSMC CMOS technology. The Simulation results show a gain of 18.2 dB, an IIP3 of −4.32 dBm and a noise figure of 3.38 dB at 2.4 GHz. The proposed LNA consumes only 967 µW from a 1-V supply.