Evidence for causality between GaN RF HEMT degradation and the EC-0.57 eV trap in GaN

The degradation of industry-supplied GaN high electron mobility transistors (HEMTs) subjected to accelerated life testing (ALT) is directly related to increases in concentrations of two defects with trap energies of E_C-0.57 and E_C-0.75 eV. Pulsed I-V measurements and constant drain current deep level transient spectroscopy were employed to evaluate the quantitative impact of each trap. The trap concentration increases were only observed in devices that showed a 1 dB drop in output power and not the result of the ALT itself indicating that these traps and primarily the E_C-0.57 eV trap are responsible for the output power degradation. Increases from the E_C-0.57 eV level were responsible for 80% of the increased knee walkout while the E_C-0.75 eV contributed only 20%. These traps are located in the drain access region, likely in the GaN buffer, and cause increased knee walkout after the application of drain voltage.     

Deep trap-induced dynamic on-resistance degradation in GaN-on-Si power MISHEMTs

Identification and characterization of a single, deep trap causing large increases in the on-resistance of GaN-on-Si power metal-insulator-semiconductor-high electron mobility transistors (MISHEMTs) is reported. This is achieved by using HEMT-based deep level optical spectroscopy (DLOS) and related methods in conjunction with high voltage off-state V_DS switching up to 400 V. A trap with an activation energy of ~ E_C − 2 eV that is physically located in the drain-access region of the MISHEMT is shown to be the primary source of an increase of the dynamic on-resistance increase by as much as ~ 9 times at 400 V operation. Comparisons of trap signatures extracted from the MISHEMT with capacitance-based DLOS measurements of simple Schottky-diode test-structures showing the same, dominant trap signature suggests that the physical defect is located within the GaN buffer and is not a surface or insulator-related defect. A buffer trap based model is presented to explain the observed on-resistance degradation effects in the MISHEMTs during high voltage switching.     

Similarities of lag phenomena and current collapse in field-plate AlGaN/GaN HEMTs with different types of buffer layers

We make a two-dimensional transient analysis of field-plate AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped semi-insulating buffer layer, which is modeled that as deep levels, only a deep acceptor located above the midgap is included (E_C − E_DA = 0.5 eV, E_C: energy level at the bottom of conduction band, E_DA: deep acceptor's energy level). And the results are compared with a case having an undoped semi-insulating buffer layer in which a deep donor above the midgap (E_C − E_DD = 0.5 eV. E_DD: the deep donor's energy level) is considered to compensate a deep acceptor below the midgap (E_DA − E_V = 0.6 eV, E_V: energy level at the top of valence band). It is shown that the drain-current responses when the drain voltage is lowered abruptly are reproduced quite similarly between the two cases with different types of buffer layers, although the time region where the slow current transients occur is a little different. The lags and current collapse are reduced by introducing a field plate. This reduction in lags and current collapse occurs because the deep acceptor's electron trapping is reduced under the gate region in the buffer layer. The dependence of drain lag, gate lag and current collapse on the field-plate length and the SiN layer thickness is also studied, indicating that the rates of drain lag, gate lag and current collapse are quantitatively quite similar between the two cases with different types of buffer layers when the deep-acceptor densities are the same.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Effects of post-annealing on the passivation interface characteristics of AlGaN/GaN high electron mobility transistors

We examined the effects of post-annealing in forming-gas ambient on the spin-on-dielectric (SOD)-buffered passivation as well as the conventional plasma-enhanced chemical vapor deposition (PECVD) Si₃N₄ passivation structure in association with the quantitative analysis of defects at the passivation interfaces of AlGaN/GaN high electron mobility transistors (HEMTs). Before the annealing, the interface state densities (D_it) of the PECVD Si₃N₄ are one-order higher (10¹²–10¹³ cm⁻² eV⁻¹) than those of the SOD SiO_x (10¹¹–10¹² cm⁻² eV⁻¹) as derived from C–V characterization. Clear reduction in D_it from the PECVD Si₃N₄ is extracted to a level of 10¹¹–10¹² cm⁻² eV⁻¹ with a stronger absorption from Si–N peak in Fourier transform infrared spectroscopy spectra after the post-annealing. On the other hand, negligible difference in D_it value is obtained from the SOD SiO_x. In this paper we propose that much lower measurement levels (~156 mA/mm) before the annealing and substantial recovery (~13% increase) after the annealing in maximum drain current density of the AlGaN/GaN HEMTs with Si₃N₄ passivations are due to the original higher density before the annealing and greater reduction in D_it of the PECVD Si₃N₄ after the annealing. Significant reduction after the annealing in gate–drain leakage current (from ~10⁻³ to ~10⁻⁵ A, 100-μm gate width) of the HEMTs with the Si₃N₄ passivation is also supposed to be attributed to the reduction of D_it.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

Drain-to-gate field engineering for improved frequency response of GaN-based HEMTs

We report on a novel approach for designing high-frequency AlGaN/GaN HEMTs based on gate-drain field engineering. This approach uses a drain-connected field controlling electrode (FCE). The devices with gate-to-FCE separation of 0.5–0.7 μm exhibit much smaller frequency behavior degradation with drain bias at least up to 30 V and yield RF gain and output power improvement up to ～2 times compared to conventional devices. These results show that the FCE is a powerful technique of improving the high-frequency, high power performance of GaN HEMTs at high drain biases.     

The role of surface barrier oxidation on AlGaN/GaN HEMTs reliability

Reliability of AlGaN/GaN HEMTs processed with different surface oxidation levels was studied using electrical and optical methods. It was found that HEMTs with more surface oxide content are more susceptible to degradation in terms of gate leakage and trapping characteristics, although this oxide layer initially passivates surface traps. In the degraded devices, trap level with activation energy of 0.45–0.47 eV was observed and attributed to surface related traps. This indicates that oxygen may play a crucial role for AlGaN/GaN HEMT reliability.     

Performance of commercial foundry-level AlGaN/GaN HEMTs after hot electron stressing

The performance degradation of commercial foundry level GaN HEMTs placed under a constant-power drain voltage step-stress test has been studied. By utilizing electroluminescence measurement techniques to optimize hot electron stress testing conditions (Meneghini, 2012), no significant permanent changes in saturation current (I_dss), transconductance (Gm), and threshold voltage (V_th) can be seen after stress testing of drain voltages from 30 V up to 200 V. We observe little permanent degradation due to hot electron effects in GaN HEMTs at these extreme operating conditions and it is inferred that other considerations, such as key dimensions in channel or peak electric field (Chynoweth, 1958; Zhang and Singh, 2001) [2,3], are more relevant to physics of failure than drain bias alone.     

Investigation of deep level defects in copper irradiated bipolar junction transistor

Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu¹¹⁺-ions with fluence of the order 10¹² ions cm^?2, is studied for radiation induced gain degradation and deep level defects. I–V measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from E_C ? 0.164 eV to E_C ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from E_V + 0.203 eV to E_V + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.     

Analysis of current collapse effect in AlGaN/GaN HEMT: Experiments and numerical simulations

In this work, current collapse effects in AlGaN/GaN HEMTs are investigated by means of measurements and two-dimensional physical simulations. According to pulsed measurements, the used devices exhibit a significant gate-lag and a less pronounced drain-lag ascribed to the presence of surface/barrier and buffer traps, respectively. As a matter of fact, two trap levels (0.45 eV and 0.78 eV) were extracted by trapping analysis based on isothermal current transient. On the other hand, 2D physical simulations suggest that the kink effect can be explained by electron trapping into barrier traps and a consequent electron emission after a certain electric-field is reached.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Reliability of 100 nm AlGaN/GaN HEMTs for mm-wave applications

The effect of gate metallization and gate shape on the reliability and RF performance of 100 nm AlGaN/GaN HEMTs on SiC substrate for mm-wave applications has been investigated under on-state DC-stress tests. By replacing the gate metallization from NiPtAu to PtAu the median time to failure at T_ch = 209 °C can be improved from 10 h to more than 1000 h. Replacing the PtAu T-gate by a spacer gate further reduces the degradation rate under on-state stress, but decreases the current-gain cut-off frequency from 75 GHz to 50 GHz. Physical failure analysis using electroluminescence and TEM cross-section revealed pit and Ni void formation at the gate foot as the main degradation mechanisms of devices with NiPtAu T-gate. High resolution EDX mapping of stressed devices indicates that the formation of pits is caused by a local aluminium oxidation process. Simulation of the stress induced changes of the input characteristics of devices with NiPtAu gate further proves the formation of pits and Ni voids.     

Investigation of deep level defects in electron irradiated indium arsenide quantum dots embedded in a gallium arsenide matrix

Gallium arsenide diodes with and without indium arsenide quantum dots were electron irradiated to investigate radiation induced defects. Baseline and quantum dot gallium arsenide pn-junction diodes were characterized by capacitance–voltage measurements, and deep level transient spectroscopy. Carrier accumulation was observed in the gallium arsenide quantum dot sample at the designed depth for the quantum dots via capacitance–voltage measurements. Prior to irradiation, a defect 0.84 eV below the conduction band (E_C – 0.84 eV) was observed in the baseline sample which is consistent with the native EL2 defect seen in gallium arsenide. After 1 MeV electron irradiation three new defects were observed in the baseline sample, labeled as E3 (E_C – 0.25 eV), E4 (E_C – 0.55 eV), and E5 (E_C – 0.76 eV), consistent with literature reports of electron irradiated gallium arsenide. Prior to irradiation, the addition of quantum dots appeared to have introduced defect levels at E_C – 0.21, E_C – 0.38, and E_C – 0.75 eV denoted as QD–DX1, QD–DX2, and QD–EL2 respectively. In the quantum dot sample after 1 MeV electron irradiation, QD–E3 (E_C – 0.28 eV), QD–E4 (E_C – 0.49 eV), and QD–EL2 (E_C – 0.72 eV) defects, similar to the baseline sample, were observed, although the trap density was dissimilar to that of the baseline sample. The quantum dot sample showed a higher density of the QD–E4 defect and a lower density of QD–E3, while the QD–EL2 defect seemed to be unaffected by electron irradiation. These findings suggest that the quantum dot sample may be more radiation tolerant to the E3 defect as compared to the baseline sample.     

Charge trapping related channel modulation instability in P-GaN gate HEMTs

In this paper, a study of the channel modulation instability of commercial p-GaN gate HEMTs is presented. During the gate-voltage stress test, substantial R_DS(ON) variations up to 78 mΩ (93.8%) were observed. It is found that the p-GaN/AlGaN/GaN gate structure enables the injection of holes and electrons, which can be captured by the donor/acceptor-like traps located in the AlGaN layer. Therefore, the trapped holes and electrons concurrently modulate the channel conductivity, resulting in R_DS(ON) variations. Device simulation was performed to help explain the mechanism from the perspective of energy band. In addition, results reveal that with the recommended working gate-voltage stress V_GS = 7 V, the on-state resistance, the threshold voltage and the off-state drain to source leakage current vary up to 8 mΩ (16.3%), 0.2 V (14.8%) and 12.8 μA (42.66%) within 1 h, respectively, which could raise reliability issues for the power electronics applications of p-GaN gate HEMTs.     

Structural,surface morphology and optical properties of sputter-coated CaCu3Ti4O12 thin film: Influence of RF magnetron sputtering power

This study focusses on the investigation of RF power variations (100–300 W) effects on structural, morphological and optical properties of CaCu₃Ti₄O₁₂ thin film deposited on ITO/glass substrate in a non-reactive atmosphere (Ar). The increase of RF power from 100 W to 300 W led to evolution of (112), (022), (033), and (224) of CCTO XRD peaks. The results indicated that all the films were polycrystalline nature with cubic structure. The crystallite size increased from 20 nm to 25 nm with increasing RF power. FESEM revealed that the films deposited were uniform, porous with granular form, while the grain size increased from 30 to 50 nm. AFM analysis confirmed the increment in surface roughness from 1.6 to 2.3 nm with increasing film grain size. Besides, optical transmittance values decreased to minimum 70% with increasing RF power while optical energy bandgap increased from 3.20 eV to 3.44 eV. Therefore, favorable CCTO thin film properties can be possibly obtained for certain application by controlling RF magnetron sputtering power.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

On the origin of dynamic Ron in commercial GaN-on-Si HEMTs

There are huge differences in dynamic on-resistance R_on, also known as current-collapse, between current GaN power HEMT technologies. Here we illustrate this fact with dynamic R_on measurements on two commercially available devices from 2 different manufacturers, with one showing more than a factor of 2 increase in dynamic R_on after OFF-state drain bias (type 1) and the other one < 15% change. HTRB stress for 1000 h and 3000 h on type 1 and type 2 respectively was found to only make subtle changes to dynamic R_on, with type 1 still showing a much larger dynamic R_on than type 2. A model for dynamic R_on is presented based on a floating, highly resistive, epitaxial buffer whose potential is determined by parasitic leakage paths. The difficulty in controlling local leakage paths can explain the problems that manufacturers are still finding in suppressing dynamic R_on.     

AlGaN/GaN Schottky barrier diodes on silicon substrates with various Fe doping concentrations in the buffer layers

This study demonstrated AlGaN/GaN Schottky barrier diodes (SBDs) for use in high-frequency, high-power, and high-temperature electronics applications. Four structures with various Fe doping concentrations in the buffer layers were investigated to suppress the leakage current and improve the breakdown voltage. The fabricated SBD with an Fe-doped AlGaN buffer layer of 8 × 10¹⁷ cm^− 3 realized the highest on-resistance (R_ON) and turn-on voltage (V_ON) because of the memory effect of Fe diffusion. The optimal device was the SBD with an Fe-doped buffer layer of 7 × 10¹⁷ cm^− 3, which exhibited a R_ON of 31.6 mΩ-cm², a V_ON of 1.2 V, a breakdown voltage of 803 V, and a buffer breakdown voltage of 758 V. Additionally, the low-frequency noise decreased when the Fe doping concentration in the buffer layer was increased. This was because the electron density in the channel exhibited the same trend as that of the Fe doping concentration in the buffer layer.