The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L₁) for a given gate length (L) are also studied and the optimum lengths L₁ under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.     

A bilayer graphene nanoribbon field-effect transistor with a dual-material gate

This paper introduces dual-material gate (DMG) configuration on a bilayer graphene nanoribbon field-effect transistor (BLGNRFET). Its device characteristics based on nonequilibrium Green׳s function (NEGF) are explored and compared with a conventional single-material gate BLGNRFET. Results reveal that an on-off ratio of up to 10 is achievable as a consequence of both higher saturation and lower leakage currents. The advantages of our proposed DMG structure mainly lie in higher carrier transport efficiency by means of enhancing initial acceleration of incoming carriers in the channel region and the suppression of short channel effects. Drain-induced barrier lowering, subthreshold swing and hot electron effect as the key short channel parameters have been improved in the DMG-based BLGNRFET.     

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.     

High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10-17A/ m, ION of 9 A/ m, ION/IOFF of 1×1011,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

基于场效应管的光电式电流传感器

提出一种新型光电式电流传感器。利用电流取样电阻将被测电流转换为电压,并利用场效应管(FET)的转移特性和发光二极管(LED)将被测电流信号转换为光强度信号,再将光信号由塑料光纤(POF)传输到光电探测器(PD),可以实现直流电流(DC)、方波脉冲电流(PC)以及工频交流电流(AC)的光学传感。综合利用FET的转移特性和PD的开路电压,并合理选择FET的静态工作点,可以实现DC的线性传感。在0.03～17.00A范围内,DC测量的非线性误差低于0.44%;方波脉冲电流响应的延迟时间约为160ns。本文提出的传感器具有响应速度快、结构简单、成本低和可实现绝缘测量等优点。     

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In_0.7Ga_0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f_T) of 113 GHz and a maximum oscillation frequency (f_max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm² device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.     

基于PVK/PbS纳米晶有机无机复合薄膜电双稳器件性能研究

通过简单旋涂方法,制备了一种基于硫化铅（PbS）纳米晶与聚乙烯基咔唑（PVK）的有机/无机复合薄膜电双稳器件,并对所制备的器件进行性能测试及其电荷传输机制研究。首先采用热注入的方法制备了尺寸均一的立方形PbS纳米晶,然后将PbS纳米晶与PVK聚合物混合作为活性层材料,制备了有机/无机复合薄膜电双稳器件。该器件展示了良好的电双稳特性并且可以实现稳定的“读-写-读-擦”操作。器件的最大电流开关比能够达到10⁴。并进一步对器件在正向电压下的I-V曲线进行了理论拟合,发现在不同电流传导状态下,器件符合不同的电传导模型。进而分析了该电双稳器件中的电荷传输机制,认为在电场的作用下,发生在纳米晶与聚合物之间的电场诱导电荷转移是产生电双稳特性的主要原因。     

Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects

In this report we focus on the performance of nanoscale double gate (DG) junctionless (JL) and inversion mode (IM) MOSFETs. The study is performed using an analytical 2-D modeling approach from our previous work and an extension for the inclusion of carrier quantization effects (QEs). The model itself is physics-based, predictive and valid in all operating regimes. Important device metrics such as the drain-induced barrier lowering (DIBL), subthreshold slope (S  ) and the _Ion/_Ioff$I_{\mathit{on}}/I_{\mathit{off}}$ ratios are in focus and discussed. The model is compared versus 2-D numerical simulation results from TCAD Sentaurus. To stand the pace with recent ITRS requirements for future CMOS technology, we target devices with a minimum channel length of 16 nm and channel thicknesses down to 3 nm. The purpose of the research is to gain knowledge about the device?s performance at such aggressively scaled dimensions.     

基于聚乙烯咔唑的非挥发型阻变存储特性分析

采用聚乙烯咔唑作为活性层构建了ITO/PVK/Al的三明治结构阻变存储元件,并对其阻变特性进行了测量。结果表明其具有明显的非挥发型双稳态阻变特性, 具有WORM存储特性。该元件具有良好的数据保持能力和耐久能力,开关态电流比可达103,且具有较低的阈值转换电压。分别对低阻态和高阻态的载流子传输机制进行了拟合, 低阻态为欧姆传导机制,高阻态为空间电荷限制电流发射机制。根据载流子传输机制, 对阻变特性进行了解释。     

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature.In this work,first,the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters.The adjusted parameters are ratio of gate and intrinsic length,gate dielectric thickness and gate work function.Secondly,the DMG (dual material gate) DG-IMOS is proposed and investigated.This DMG DG-IMOS is further optimized to obtain the best possible performance parameters.Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS,shows better ION,ION/IOFF ratio,and RF parameters.Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS,optimized performance is achieved including ION/IoFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10-4 A/μm and transconductance of 1.06 × 10-3 S/μm.It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.     

低导通电阻和栅漏电的高性能InAlN/GaN HEMT

本文制备了100nm栅长的InAlN/GaN HEMT。通过氧处理和优化欧姆接触获得了高性能的InAlN/GaN HEMT。所制备的器件在栅压偏置为2V时,漏端输出电流密度达到2.18A/mm。器件的导通电阻为1.49Ω*mm。与常规器件相比,器件的栅漏电下降了两个数量级。器件也获得良好的射频特性,电流截止频率和最高震荡频率分别为81GHz和138GHz。根据现有的报道,这是国内较早报道GaN基HEMT电流密度超过2A/mm。     

Design,modelling, and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors (FGT) with a novel built-in security feature. The new device has applications in guarding the IC chips against the current reverse engineering techniques, including scanning capacitance microscopy (SCM). The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate, even in nano-meter scales. The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate. This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic. Furthermore, this model was verified with a simulation. In addition, the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor. The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated. Finally, the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.     

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.     

PECVD a—Si：H薄膜对TFT有源矩阵性能的影响及其淀积工艺研究

分析了a－Si：HTFT有源层──a－Si：H薄膜质量和厚度对于a－Si：HTFT关键性指标（通断电流比、阈值电压、响应时间、开口率）的影响，深入、详细地研究了PECVD衬底温度、RF功率和频率、气体流量和反应室气压等淀积工艺参数对a—Si：H薄膜组分、结构的影响，并在实验的基础上给出了它们之间的关系曲线，确定了最佳淀积工艺参数，从而获得了高性能的7.5cm372×276象素a－Si：HTFT有源矩阵。     

Influence of low-field-mobility-related issues on SiC metal-semiconductor field-effect transistor performance

High field-dependent electron transport characteristics in 4H-SiC were measured successfully using a nanosecond-pulsed technique. It should be noted that the velocity-field characteristics of SiC are different from GaAs in that SiC does not have velocity overshooting behavior. Without the overshooting behavior, the current density of SiC metal-semiconductor field-effect transistors (MESFETs) is restricted fundamentally by the low drift velocity in the low-field, parasitic regions. These parasitic regions not only limit the current density but also are responsible for a significant shift of the threshold voltage.     

一种基于聚合物绝缘层的TIPS-pentacene晶体管性质研究

采用顶接触结构研究制备了以TIPS-pentacene为有源层、聚甲基丙烯酸甲酯(PMMA)为绝缘层的有机场效应晶体管(OFET),其中绝缘层采用溶液旋涂法制备,电极采用Au电极。通过原子力显微镜(AFM)和X射线衍射(XRD)技术对TIPS-pentacene在PMMA上的生长特性进行了详细分析,结果表明,器件获得了良好的电学特性,其场效应迁移率、阈值电压以及开关电流比分别为0.137 cm2/Vs、-19 V和9.74×104。对器件的稳定性也做了详细研究。     

A study on the electrical characteristics of InGaZnO thin-film transistor with HfLaO gate dielectric annealed in different gases

The effects of dielectric-annealing gas (O₂, N₂ and NH₃) on the electrical characteristics of amorphous InGaZnO thin-film transistor with HfLaO gate dielectric are studied in-depth, and improvements in device performance by the dielectric annealing are observed for each gas. Among the samples, the N₂-annealed sample has a high saturation carrier mobility of 35.1 cm²/V s, the lowest subthreshold swing of 0.206 V/dec and a negligible hysteresis. On the contrary, the O₂-annealed sample shows poorer performance (e.g. saturation carrier mobility of 15.7 cm²/V s, larger threshold voltage, larger subthreshold swing of 0.231 V/dec and larger hysteresis), which is due to the decrease of electron concentration in InGaZnO associated with the filling of oxygen vacancies by oxygen atoms. Furthermore, the NH₃-annealed sample displays the lowest threshold voltage (1.95 V), which is attributed to the increased gate-oxide capacitance and introduced positive oxide charges. This sample also reveals a change in the dominant trap type due to the over-reduction of acceptor-like border and interface traps, as demonstrated by a hysteresis phenomenon in the opposite direction. Lastly, the low-frequency noise of the samples has also been studied to support the analysis based on their electrical characteristics.     

基于SOA-XGM效应的双逻辑门叠加结构研究

为了提高光传输系统数据信息的机密性与安全性,开展了光传输系统物理层全光加/解密技术的理论分析,设计了全光AB逻辑实验方案,通过结构相同的两全光AB逻辑门输出信号的耦合,实验实现了对速率为10Gb/s的明文光信号的全光加密。     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.