Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories

In memory technology, size reduction induces consequences in terms of reliability, including an increase in the line resistances and a voltage drop along the line during memory operation. This problem can occur in Flash products during sector erase mode, and in resistive RAM (ReRAM) during forming, reset or word-reading modes.In this paper we apply a simple resistive model to determine the wordline (or bitline) length of a Flash memory (and thus to optimize the Flash memory array's size) or the word length of a ReRAM, according to specific reliability criteria: the threshold voltage drop of cells along a line in a Flash memory sector, or the resistance variation of the cells in a ReRAM word.For the technologies considered in this paper, on the one hand we demonstrate a maximal threshold voltage drop of 2 V for a 4 Gbit Flash array and we provide design recommendations, and on the other hand we demonstrate that a maximal word length of 32 bits for ReRAM can be achievable in a ReRAM matrix. The presented methodology can easily be extended to any memory technology.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Influence of Sn content on properties of ZnO:SnO2 thin films deposited by ultrasonic spray pyrolysis

The present work is devoted to the preparation of zinc oxide (ZnO): tin oxide (SnO₂) thin films by ultrasonic spray technique. A set of films are deposited using a solution formed with zinc acetate and tin chloride salts mixture with varied weight ratio R=[Sn/(Zn+Sn)]. The ratio R is varied from 0 to 100% in order to investigate the influence of Sn concentration on the physical properties of ZnO:SnO₂ films. The X rays diffraction (XRD) analysis indicated that films are composed of ZnO and SnO₂ distinct phases without any alloys or spinnel phase formations. The average grain size of crystallites varies with the ratio R from 17 to 20 nm for SnO₂ and from 24 to 40 nm for ZnO. The obtained films are highly transparent with a transmission coefficient equal to 80%. An increase in Sn concentration increases both the effective band gap energy from 3.2 to 4.01 eV and the photoluminescence intensity peak assigned defects to SnO₂. The films electrical characterization indicated that films are resistive. Their resistivities vary between 1.2×10² and 3.3×10⁴ (Ω cm). The higher resistivity is measured in film deposited with a ratio R equal to 50%.     

Enhanced organic ferroelectric field effect transistor characteristics with strained poly(vinylidene fluoride-trifluoroethylene) dielectric

Poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%) was used as the functional dielectric layer in organic ferroelectric field effect transistors (FeFET) for non-volatile memory applications. Thin P(VDF-TrFE) film samples spin-coated on metallized plastic substrates were stretch-annealed to attain a topographically flat-grain structure and greatly reduce the surface roughness and current leakage of semi-crystalline copolymer film, while enhancing the preferred β-phase of the ferroelectric films. Resultant ferroelectric properties (P_R = |10| μC/cm², E_C = |50| MV/m) for samples simultaneously stretched (50–70% strain) and heated below the Curie transition (70 ^oC) were comparable to those resulting from high temperature annealing (>140 ^oC). The observed enhancements by heating and stretching were studied by vibration spectroscopy and showed mutual complementary effects of both processes. Organic FeFET fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE) films showed substantial improvement of semiconductor grain growth and enhanced electrical characteristics with promising non-volatile memory functionality.     

Characterization of ZrTiO4 thin films prepared by sol–gel method

The electrical properties, memory switching behavior, and microstructures of ZrTiO₄ thin films prepared by sol–gel method at different annealing temperatures were investigated. All films exhibited ZrTiO₄ (111) and (101) orientations perpendicular to the substrate surface, and the grain size increased with increasing annealing temperature. A low leakage current density of 1.47×10^?6 A/cm² was obtained for the prepared films. The I–V characteristics of ZrTiO₄ capacitors can be explained in terms of ohmic conduction in the low electric field region and Schottky emission in the high electric field region. An on/off ratio of 10² was measured in our glass/ITO/ZrTiO₄/Pt structure with an annealing temperature of 600 °C. Considering the primary memory switching behavior of ZrTiO₄, ReRAM based on ZrTiO₄ shows promise for future nonvolatile memory applications.     

AlGaN/GaN Schottky barrier diodes on silicon substrates with various Fe doping concentrations in the buffer layers

This study demonstrated AlGaN/GaN Schottky barrier diodes (SBDs) for use in high-frequency, high-power, and high-temperature electronics applications. Four structures with various Fe doping concentrations in the buffer layers were investigated to suppress the leakage current and improve the breakdown voltage. The fabricated SBD with an Fe-doped AlGaN buffer layer of 8 × 10¹⁷ cm^− 3 realized the highest on-resistance (R_ON) and turn-on voltage (V_ON) because of the memory effect of Fe diffusion. The optimal device was the SBD with an Fe-doped buffer layer of 7 × 10¹⁷ cm^− 3, which exhibited a R_ON of 31.6 mΩ-cm², a V_ON of 1.2 V, a breakdown voltage of 803 V, and a buffer breakdown voltage of 758 V. Additionally, the low-frequency noise decreased when the Fe doping concentration in the buffer layer was increased. This was because the electron density in the channel exhibited the same trend as that of the Fe doping concentration in the buffer layer.     

Side chains contributions to characteristics of resistive memory based on water-soluble polyfluorenes: Effects of structure and length of side pendant group

This paper investigates the effects of side chains, which are important structural constituents, on the characteristics of organic resistive memory devices with water-soluble polyfluorene (WPF) derivatives. The WPF derivatives have either an ethylene oxide (EO) or an alkyl side chain the lengths of the EO side chains are 2, 4, or 6 molecules. WPFs exhibit typical bipolar switching behaviors with reliable non-volatile characteristics and good device-to-device uniformity under ambient conditions. WPFs with the EO side chains showed better memory characteristics than those of the alkyl side chains of similar length. In addition, as the EO unit lengthened, the ON/OFF ratio of the memory device gradually increased from 5 × 10² to 10⁵, and the threshold voltage (V_th) progressively decreased from 4 to 3.5 V. The retention times for WPF-hexyl, WPF-2O, WPF-4O, and WPF-6O are 10⁴, 200, 10⁴, and 10⁴ s, respectively. The excellent switching properties of WPF-4O and WPF-6O are believed to be mainly attributed to highly localized current pathways and the low trap density.     

High-resolution transmission electron microscopy study on bipolar resistive switching behavior in TiO2 thin films

We fabricated TiO₂ thin films the by sol–gel process. Successful I–V curves can be obtained in the Cu/TiO₂/ATO structure device in which TiO₂ thin film was calcined at 300 °C. The bipolar resistive switching behavior was observed and the ratio of R_off/R_on can be increased to 10⁴. The switching voltage changes from 4.8 to 3.5 V when the current compliance drops from 10 to 0.1 mA. We also investigated the microstructure by HRTEM technology.     

High photosensitivity with enhanced photoelectrical contribution in hybrid nanocomposite flexible UV photodetector

To devise a reliable strategy to develop an ultraviolet (UV) sensitive hybrid photodetector, plasma process is utilized as a single step method for production of large area nanocomposite films based on plasma polymerized aniline–titanium dioxide (PPani–TiO₂). The synthesis of PPani–TiO₂ nanocomposite films are made using reactive magnetron sputtering in combination with plasma polymerization. The deposited PPani–TiO₂ nanocomposite films are characterized and discussed in terms of structural, optical and electrochemical properties. A hybrid flexible nanostructured UV photodetector is constructed from PPani–TiO₂ nanocomposite and its optoelectronic properties are evaluated which exhibits a greatly enhanced photosensitivity resulting in high photoconductive gain (G = 4.56 × 10⁴) and high responsivity (R = 9.36 × 10³ AW⁻¹) under UV illumination of 254 nm. The flexible devices are successfully operated under bending up to 170° (bending radius, R = 8 mm) and showed a good folding strength and stability. The proposed plasma based method provides a green technology where the self-assembly of molecules, that is, the spontaneous association of atomic or molecular building blocks under plasma environment, emerge as a successful strategy to form well-defined structural and morphological units of nanometer dimensions.     

Enhanced carrier mobility and photon-harvesting property by introducing Au nano-particles in bulk heterojunction photovoltaic cells

In this study, polymer solar cells (PSCs) doped with Au nanoparticles (Au NPs) were successfully fabricated to maximize the photon-harvesting properties on the photoactive layer. In addition, a conductivity-enhanced hybrid buffer layer was introduced to improve the photon absorption properties and effectively separate the generated charges by adding Au NPs and dimethylsulfoxide (DMSO) to the PH 500 as a buffer layer. The PSC performance was optimized with a 88% improvement over the conventional PSCs (photoactive area: 225 mm², power conversion efficiency (PCE): 3.2%) by the introduction to the buffer layer of Au NPs and DMSO at 10 wt% and 1.0 wt%, respectively, and with 15 wt% Au NP doping in the photoactive layer. The internal resistance was decreased due to the increased photocurrent caused by the localized surface plasmon resonance (LSPR) effect of the Au NPs in the photoactive layer and by the improvement of carrier mobility induced by the DMSO doping of the buffer layer. As a result, the series resistance (R_S) deceased from 42.3 to 19.7 Ω cm² while the shunt resistance (R_SH) increased from 339 to 487 Ω cm².     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Facile synthetic route to implement a fully bendable organic metal–insulator–semiconductor device on polyimide sheet

Triblock copolymer surfactant, HO(CH₂CH₂O)₂₀(CH₂CH(CH₃)O)₇₀(CH₂CH₂O)₂₀H (i.e. P123)-based nanocrystalline (nc)-TiO₂ thin film had been synthesized on organic flexible polyimide (PI) sheet for their application in organic metal–insulator–semiconductor (MIS) device. The nc-TiO₂ film over PI was successfully deposited for the first time by a systematic solution proceeds dip-coating method and by the assistance of triblock copolymer surfactant. The effect of annealing temperature (270 °C, 5 h) on the texture, morphology and time-induced hydrophilicity was studied by X-ray diffraction (XRD), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and contact angle system, respectively, to examine the chemical composition of the film and the contact angle. The surface morphology of the semiconducting layer of organic pentacene was also investigated by using AFM and XRD, and confirmed that continuous crystalline film growth had occurred on the nc-TiO₂ surface over flexible PI sheet. The semiconductor–dielectric interface of pentacene and nc-TiO₂ films was characterized by current–voltage and capacitance–voltage measurements. This interface measurement in cross-link MIS structured device yielded a low leakage current density of 8.7 × 10^?12 A cm^?2 at 0 to ?5 V, maximum capacitance of 102.3 pF at 1 MHz and estimated dielectric constant value of 28.8. Furthermore, assessment of quality study of nc-TiO₂ film in real-life flexibility tests for different types of bending settings with high durability (c.a. 30 days) demonstrated a better comprehension of dielectric properties over flexible PI sheet. We expected them to have a keen interest in the scientific study, which could be an alternate opportunity to the excellent dielectric–semiconductor interface at economic and low temperature processing for large-area flexible field-effect transistors and sensors.     

Properties of fluorine-doped tin oxide films prepared by an improved sol-gel process

Fluorine-doped tin oxide (FTO) films were prepared by an improved sol-gel process, in which FTO films were deposited on glass substrates using evaporation method, with the precursors prepared by the conventional sol-gel method. The coating and sintering processes were combined in the evaporation method, with the advantage of reduced probability of films cracking and simplified preparation process. The effects of F-doping contents and structure of films on properties of films were analyzed. The results showed the performance index (Φ_TC=3.535×10⁻³ Ω⁻¹ cm) of the film was maximum with surface resistance (R_sh) of 14.7 Ω cm⁻¹, average transmittance (T) of 74.4% when F/Sn=14 mol%, the reaction temperature of the sol was 50 °C, and the evaporation temperature was 600 °C in muffle furnace, and the film has densification pyramid morphology and SnO_2−xF_x polycrystalline structure with tetragonal rutile phase. Compared with the commercial FTO films (Φ_TC=3.9×10⁻³ Ω⁻¹ cm, R_sh=27.4 Ω cm⁻¹, T=80%) produced by chemical vapor deposition (CVD) method, the Φ_TC value of FTO films prepared by an improved sol-gel process is close to them, the electrical properties are higher, and the optical properties are lower.     

On the origin of dynamic Ron in commercial GaN-on-Si HEMTs

There are huge differences in dynamic on-resistance R_on, also known as current-collapse, between current GaN power HEMT technologies. Here we illustrate this fact with dynamic R_on measurements on two commercially available devices from 2 different manufacturers, with one showing more than a factor of 2 increase in dynamic R_on after OFF-state drain bias (type 1) and the other one < 15% change. HTRB stress for 1000 h and 3000 h on type 1 and type 2 respectively was found to only make subtle changes to dynamic R_on, with type 1 still showing a much larger dynamic R_on than type 2. A model for dynamic R_on is presented based on a floating, highly resistive, epitaxial buffer whose potential is determined by parasitic leakage paths. The difficulty in controlling local leakage paths can explain the problems that manufacturers are still finding in suppressing dynamic R_on.     

Contact resistivity of amorphous and crystalline GeCu2Te3 to W electrode for phase change random access memory

We have investigated the contact resistivity of GeCu₂Te₃ (GCT) phase change material to a W electrode using the circular transfer length method (CTLM). The contact resistivity ρ_c of as-deposited amorphous GCT to W was 3.9×10⁻² Ω cm². The value of ρ_c drastically decreased upon crystallization and crystalline GCT that annealed at 300 °C showed a ρ_c of 4.8×10⁻⁶ Ω cm². The ρ_c contrast between amorphous (as-deposited) and crystalline (annealed at 300 °C) states was larger in GCT than in conventional Ge₂Sb₂Te₅ (GST). Consequently, it was suggested from a calculation based on a simple vertical structure memory cell model that a GCT memory cell shows a four times larger resistance contrast than a GST memory cell.     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.     

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/Al device

The dark current density–voltage characteristic of Au/ZnPc/Al device at room temperature has been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to be ohmic, while at high voltages, space charge limited the current mechanism dominated by exponential trapping levels. Junction parameters such as rectification ratio (RR), series resistance (R_s), and shunt resistance (R_sh) were found to be 9.42, 9.72 MΩ, and 0.88 × 10³ MΩ, respectively. The current density–voltage characteristics under white light illumination (100 W/m²) gives values of 0.55 V, 3 × 10⁻³ A/m², 0.18 and 5.8 × 10⁻⁴% for the open circuit voltage, V_oc, the short circuit current density (J_sc), the fill factor (FF), and conversion efficiency (η), respectively.     

Nonvolatile memory performance improvements for solution-processed thin-film transistors with composition-modified In–Zn–Ti–O active channel and ferroelectric copolymer gate insulator

The nonvolatile memory thin-film transistors (M-TFTs) using a solution-processed indium-zinc-titanium oxide (IZTiO) active channel and a poly(vinylidene fluoride-trifluoroethylene) ferroelectric gate insulator were fabricated and characterized to elucidate the relationships between the IZTiO channel composition and the memory performances such as program speed and data retention. The compositions of the spin-coated IZTiO layers were modified with different Ti amounts of 0, 2, 5, and 10 mol%. The carrier concentration of IZTiO channel layer was effectively modulated by the incorporated Ti amounts and the defect densities within the channel were effectively reduced by Ti incorporation. The M-TFT fabricated with IZTiO channel with 2-mol% Ti composition exhibited the best overall device performances, in which the μ_FE, SS, MW, and programmed I_on/off were obtained to be 23.6 cm² V^?1 s^?1, 701 mV/decade, 11.8 V, and 1.2 × 10⁵, respectively. Furthermore, thanks to the suitable amounts of Ti incorporation into the IZO, the improved program speed and data retention properties were successfully confirmed.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Effect of fullerene doping on the electrical properties of P3HT/PCBM layers

Poly (3-hexylthiophene-2, 5-diyl) (P3HT) and its blend with Phenyl-C₆₁-Butyric acid-Methyl-Ester (PCBM) and fullerene (C₆₀) thin films were prepared and their electrical properties for memory applications were studied. Due to doping, a sharp decrease in the resistance for a P3HT:PCBM:C₆₀ device was observed at around 70 °C which makes it useful for thermal switching applications. Addition of C₆₀ to P3HT:PCBM blend gave a high value for R_RESET/R_SET in thermal switching. For bias switching, threshold voltage reduces to 1.4 V from 25 V with the addition of C₆₀ to P3HT layer.