The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

超薄高介电Er2O3栅介质薄膜的漏电机理

采用激光分子束外延设备在不同温度下制备了不同厚度的超薄晶态、非晶态高介电Er2O3栅介质薄膜,用X射线衍射和高分辨透射电镜分析了薄膜结构,用HP4142B半导体参数分析仪测试了Al/Er2O3/Si/Al结构MOS电容器的漏电流。XRD谱和HRTEM图像显示400℃以下制备的Er2O3薄膜呈非晶态,400℃到840℃制备的Er2O3薄膜是(111)方向高度择优取向的。电学测试表明：晶态Er2O3薄膜厚度由5.7 nm 减小到3.8 nm,漏电流密度从6.20×10-5 A/cm2突增到6.56×10-4 A/cm2,增加了一个数量级。而厚度3.8 nm的非晶Er2O3薄膜漏电流密度仅为1.73×10-5 A/cm2。漏电流数据分析显示高场下超薄Er2O3薄膜的漏电流主要来自于Fowler-Nordheim隧穿。低场下超薄晶态Er2O3薄膜较大的漏电流是由晶粒边界产生的杂质缺陷引起。     

La2O3 gate dielectrics for AlGaN/GaN HEMT

The annealing temperature dependent electrical characteristics of La₂O₃ gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (V_th) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La₂O₃ and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La₂O₃ film, which is useful to limit the reduction in gate capacitance. A high k-value for La₂O₃ gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.     

Degradation of high-K LA2O3 gate dielectrics using progressive electrical stress

The evolution of the leakage current in high-K lanthanum oxide films in MOS devices caused by the application of progressive electrical stress is investigated. The degradation method consists in performing successive voltage sweeps using an ever increasing voltage range with the aim of generating incremental damage to the structure in a controlled manner. We show that the total current flowing through the device can be thought of as formed by two parallel components, one associated with the tunneling mechanism and the other one associated with diode-like conduction. This latter component evolves with applied stress. It is shown the importance of considering series and parallel resistances in order to account for the right shape of the conduction characteristics. Analytical expressions for both current contributions suitable for all stages of degradation and bias conditions are provided.     

Electrical characteristics of MOSFETs with La2O3/Y2O3 gate stack

A metal oxide semiconductor field effect transistor (MOSFET) with ultra-thin La₂O₃/Y₂O₃ high-k gate dielectric was fabricated. The effects of thermal treatment process on both physical and electrical characteristics of the La₂O₃/Y₂O₃ stack were studied using XPS and electrical measurements. It was observed that the effective mobility of the fabricated MOSFETs with La₂O₃/Y₂O₃ gate stack was not degraded with increasing the annealing temperatures up to 600 °C. X-ray photoelectron spectroscopy (XPS) analysis also revealed that the formation of SiO₂ and silicate layer at the interface was suppressed in La₂O₃/Y₂O₃ stack compare to that of in La₂O₃ single layer. Obtained results suggesting that La₂O₃/Y₂O₃ gate stack is one of the promising candidates for high-k gate insulator to be used in the future metal oxide field effect transistors.     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

1 Volt organic transistors with mixed self-assembled monolayer/Al2O3 gate dielectrics

Control of the threshold voltage and the subthreshold swing is critical for low voltage transistor operation. In this contribution, organic field-effect transistors (OFETs) operating at 1 V using ultra-thin (∼4 nm), self-assembled monolayer (SAM) modified aluminium oxide layers as the gate dielectric are demonstrated. A solution-processed donor–acceptor semiconducting polymer poly(3,6-di(2-thien-5-yl)-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione)thieno[3,2-b]thiophene) (PDPP2TTT) is used as the active layer. It is shown that the threshold voltage of the fabricated transistors can be simply tuned by carefully controlling the composition of the applied SAM. The optimised OFETs display threshold voltages around 0 V, low subthreshold slopes (150 ± 5 mV/dec), operate with negligible hysteresis and show average saturated field-effect mobilities in excess of 0.1 cm²/V s at 1 V.     

Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La₂O₃/ZrO₂ high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10¹¹ eV⁻¹ cm⁻², a low subthreshold slope of 70-80 mV/decade, and an I_ON/I_OFF current ratio greater than 2 × 10⁶ are obtained.     

Modeling of direct tunneling current through interfacial oxide and high-K gate stacks

In this paper, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (1 0 0) Si substrate through interfacial SiO₂ and high-K gate stacks. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experimental data. For the same effective oxide thickness (EOT) of 2 nm, the direct tunneling current of a HfO₂ high-K dielectric (6.4 nm, K_f=25) overlaying a 1 nm thermal oxide is reduced by four orders of magnitude compared with a pure SiO₂ film at low gate voltages. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltages.     

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si/sub 3/N/sub 4//SiO/sub 2/, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement.     

Sb_2O_3掺杂Ba(Ti_(0.91)Zr_(0.09))O_3陶瓷的结构与性能

采用固相反应法制备了Sb2O3掺杂的Ba(Ti0.91Zr0.09)O3陶瓷,研究了Sb2O3掺杂量(x(Sb2O3)为0.5%～5.0%)对陶瓷晶相结构及介电性能的影响,分析了陶瓷电滞回线变化的原因。结果表明:Sb3+进入了Ba(Ti0.91Zr0.09)O3陶瓷晶格,引起晶格畸变,且无第二相出现。随着Sb2O3掺杂量的增加,陶瓷晶粒逐渐变小变均匀,tanδ减小。Sb2O3掺杂的Ba(Ti0.91Zr0.09)O3陶瓷为弥散相变铁电体,在x(Sb2O3)为3.0%处弥散程度最小。     

氧化钇掺杂NBBT压电陶瓷的介电特性

研究了Y2O3掺杂对(Na0.5Bi0.5)0.94Ba0.06TiO3(NBBT)陶瓷晶体结构、介电性能与介电弛豫行为的影响。XRD分析表明,x(Y2O3)掺杂在0～0.7%范围内陶瓷均能够形成纯钙钛矿固溶体。修正的居里-外斯公式较好地描述了陶瓷弥散相变特征,弥散指数随Y2O3掺杂量的增加先下降后增加。Y2O3掺杂量低于0.3%的陶瓷仅在低温介电反常峰tf附近表现出明显的频率依赖性,Y2O3掺杂量高于0.5%的陶瓷材料在室温和tf之间都表现出明显的频率依赖性。根据宏畴-微畴转变理论探讨了该体系陶瓷介电弛豫特性的机理。     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.     

Improving channel carrier mobility and immunity to charge trapping of high-K NMOSFET by using stacked Y/sub 2/O/sub 3//HfO/sub 2/ gate dielectric

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.