Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance

The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.     

深亚微米MOSFET二维数值模拟的若干结果

对溶亚微米器件，由于工作电压下降，要求重新确定ＬＤＤ和常规ＭＯＳＦＥＴ在ＶＬＳＩ中的作用。本文从基本器件数理方程发出，对深亚微米常规及ＬＤＤ ＭＯＳＦＥＴ的器件特性、热载流子效应及短沟道效应进行了二维稳态数值模拟，指出了常规和ＬＤＤ ＭＯＳＦＥＴ各自的局限性，明确了在深亚微米ＶＬＳＩ中，ＬＤＤ仍然起主要作用。     

Gate length scalability of n-MOSFETs down to 30 nm: Comparisonbetween LDD and non-LDD structures

Gate length scalability of LDD and non-LDD n-MOSFETs are investigated in terms of resistance to short-channel effects. Extremely small gate electrodes are delineated using electron beam direct writing and highly selective dry-etching techniques. An LDD MOSFET with As-implanted 15-nm-deep junctions shows a superior scalability down to 30 nm. In contrast, in the case of a non-LDD MOSFET having Sb-δ-doped 18-nm-deep junctions, the drain induced barrier lowering (DIBL) mechanism limits the minimum gate length to around 80 nm, at which favorable device operation is achieved. The difference between built in potential of source/drain junctions (around 0.1 eV) of LDD and non-LDD devices is found to remarkably affect short channel characteristics in the sub-0.1-μm region     

A manufacturing sensitivity analysis of 0.35 μm LDD MOSFET's

Fundamental to successful manufacturing of integrated circuits is the achievement of sufficient control in all process steps to realize, with very high yield, fully functional circuits whose performance and reliability conform to pre-determined standards. Towards this end, it is increasingly necessary to relate in a quantitative manner the sensitivity of the electrical performance of the final devices and circuits to variations in structural parameters and doping profiles, which in turn can be related to process and tool performance variations. In this paper, we describe the results of an analysis performed to quantify the sensitivity of the electrical parameters of a 0.35 μm LDD MOSFET to variations in the doping and structural parameters of the device that are anticipated in manufacturing. A central-composite design was used to develop second-order models for six key device electrical parameters. The resulting models are manifested as second-order equations relating the device electrical parameter variations to random variations in seven key device structure and doping parameters. This set of equations thus allows one to understand quantitatively the source and nature of the device electrical parameter variations. A simple Monte Carlo approach is applied to predict the statistical distributions of the key device electrical parameters which result from the random manufacturing variations in the structure and doping parameters by using the quantitative relationships developed in this paper     

Reply to "Comments on 'structure-enhanced MOSFET degradation due to hot-electron injection'"

The equal-substrate-current stressing condition used to compare hot-electron-induced MOSFET degradation in different device structures is discussed. The error introduced by using this stressing condition is quantitatively assessed and shown to be too small to affect the interpretation of the experimental data. The post-stress transconductance degradation characterisitics in LDD MOSFET's are also discussed.     

Effects of source/drain implants on short-channel MOSFET I-V andC-V characteristics

The effects of source/drain implants on n-channel MOSFET I-V and C-V characteristics are measured and compared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substantial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced V_TH roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the device/circuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法,建立了适用于亚微米、深亚微米的LDD MOSFET输出I-V特性解析模型,模型中重点考虑了衬底电流的作用.模拟结果与实验有很好的一致性.该解析模型计算简便,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述,因此适用于器件的优化设计及可靠性分析.     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法 ,建立了适用于亚微米、深亚微米的 L DD MOSFET输出 I- V特性解析模型 ,模型中重点考虑了衬底电流的作用 .模拟结果与实验有很好的一致性 .该解析模型计算简便 ,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述 ,因此适用于器件的优化设计及可靠性分析     

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFET's is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFET's.     

Source-and-drain series resistance of LDD MOSFET's

The introduction of n- regions makes an LDD MOSFET behave differently from a conventional MOSFET. The source-and-drain series resistance, which consists of the n+-and-n-regions, shows a strong dependence on the gate bias. Also, the apparent effective length can vary with gate bias. These special features cause the traditional method to determine effective channel length and series resistance inapplicable. In this letter, we propose a method to determine the "intrinsic" channel length and gate-voltage-dependent source-and-drain series resistance of an LDD MOSFET and a modal for the LDD device current at small drain-source voltage.     

An analytic I—V model for lightly doped drain (LDD) MOSFET devices

An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n^-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.     

Asymmetrical characteristics in LDD and minimum-overlap MOSFET's

An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the I-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive level angle.     

轻掺杂漏(LDD)MOSFET的数值模拟

轻掺杂漏(LDD)MOSFET是一种已用在VLSI中的新型MOSFET结构.为了有效地进行LDD MOSFEI的优化设计,我们在二维数值模拟器MINIMOS的基础上,修改了边界条件及输入输出格式,考虑了轻掺杂区的杂质分布,研制成功了一种既适用于常规以MOSFET,又适用于LDD MOSFET的二维数值模拟程序FD-MINIMOS.应用该程序对LDD MOSFET的一系列直流特性模拟的结果表明,不同的轻掺杂浓度对于抑制沟道电场及热电子效应具有不同的效果,为轻掺杂区优化设计提供了重要信息.     

MOSFET drain engineering analysis for deep-submicrometerdimensions: a new structural approach

A new MOS transistor structural approach (hot-carrier-induced MOSFET) capable of substantially suppressing adverse hot-carrier effects, while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFETs (L _gate⩽0.35 μm) is described. This structure is unique in having a lower doped N^- region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFETs have an N^- region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions     

Full-band Monte Carlo investigation of hot carrier trends in thescaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated     

Scanning probe microscopy in semiconductor failure analysis

Scanning probe microscopy (SPM) is still a relatively new tool in semiconductor failure analysis (FA). But within the last few years it has developed into an essential imaging method for process control and failure analysis due to its unique features and high adaptability. Atomic force microscopy is indispensable whenever three-dimensional and quantitative surface information combined with unsurpassed resolution is needed. New electrical SPM techniques offer previously inaccessible insights into the nanoscopic construction of semiconductors. They provide for the first time two-dimensional maps of various physical parameters like oxide thickness, doping, temperature or current at sub-micron to nanometer resolution. By this SPM greatly enhances the possibilities of FA to find faults and control processes.     

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

LDD注入工艺对40 nm 中压NMOS器件HCI-GIDL效应的优化

基于40 nm CMOS工艺,研究了8 V MV NMOS器件的HCI-GIDL效应的优化。分析了增大LDD注入倾角、二次LDD注入由P注入变为As注入两种措施对电学特性的影响。测试结果表明,两种措施均对器件的衬底电流、关态泄漏电流产生较好效果。利用TCAD工具,模拟了LDD注入工艺的优化对掺杂形貌、电场分布和碰撞电离强度的影响。分析了HCI-GIDL效应得以优化的物理机制。     

适于器件及电路分析的全耗尽短沟道LDD／LDSSOI MOSFET器件模型

本文系统描述了全耗尽短沟道ＬＤＤ／ＬＤＳＳＯＩＭＯＳＦＥＴ器件模型的电压电压特性。该模型扩展了我们原有的薄膜全耗尽ＳＯＩＭＯＳＦＥＴ模型，文中着重分析了器件进入饱和区后出现的沟道长度调制效应，及由于ＬＤＤ／ＬＤＳ区的存在对本征ＭＯＳ器件电流特性的影响。     

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

Analytical model for the transconductance, cut off frequency, transit time and fringing capacitance of LDD MOSFETs is presented with a simple approach. The analysis is carried out considering the LDD device as a conventional MOSFET with a series resistance [Z.-H. Liu et al., Threshold voltage model for submicrometer MOSFETs. IEEE Trans Electron Devices 1993; ED-40: 86–94] and a simple closed form expressions for cut off frequency and transit time is obtained. The total gate capacitance, i.e. the geometric and fringing capacitance, is calculated for both LDD and non-LDD devices and lower fringing capacitance is reported in LDD devices. Lower cut-off frequencies and higher transit time are reported in LDD devices for the same channel length.