Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies

Bulk-driven MOS transistors lead to a compact low-voltage/low-power input stage implementation. This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced to point out some limitations inherent in multiple-pair input stages and carry out performance comparison, based on experimental data obtained in standard 0.35 μm CMOS technology. The performance achieved by the single-pair bulk-driven input stage can be readily extended to a nanoscale process, as lower supply voltages in scaled technologies are expected. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage and show intrinsic advantages of this approach in some amplifier features, such as linearity and common-mode rejection ratio, as compared to the case of the composite solution.     

A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps

A simple dynamic biasing scheme to extend the input/output range of cascode amplifiers is introduced. It requires minimum extra hardware and no additional power consumption. A dynamic biased telescopic op-amp is discussed as an application example. Experimental results of a fabricated test chip in 0.5 μm CMOS technology are presented that verify the proposed technique.     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

Design tradeoffs for sub-mW CMOS biomedical limiting amplifiers

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35 μm CMOS technology to operate over dc to 20 MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 72 dB.     

Very Low Voltage Rail-to-Rail Programmable-Gain CMOS Amplifier

A novel design technique for operating closed-loop amplifier circuits at very low supply voltages is proposed. It is based on the use of quasi-floating gate transistors, avoiding issues encountered in true floating-gate structures such as the initial floating-gate charge, offset drift with temperature, and the gain-bandwidth product degradation. A programmable-gain differential amplifier is designed and implemented following this method. Measurement results of an experimental prototype fabricated in a 0.5-m CMOS technology validate on silicon the proposed technique.     

Low-Voltage Current Feedback Operational Amplifiers

A number of current feedback operational amplifier topologies suitable for operation in a low-voltage environment are introduced in this paper. Their realization is based on the corresponding low-voltage second generation current conveyor topologies. Important performance factors such as accuracy, bandwidth, and linearity have been considered, and the obtained simulation results have been compared in order to evaluate the behavior of the proposed topologies.     

CMOS Power-Efficient Buffers and Amplifiers

In this paper, some topologies of novel power-efficient single-ended and fully differential amplifiers and buffers are presented. The reduction of the power dissipation has been ensured through the application of an adaptive biasing architecture which gives a current dependent on the input differential voltage. This allows the minimization of the stand-by power consumption without affecting the transient characteristics. The proposed topology, implemented in a standard CMOS technology, has been applied in the design of input and output stages of low-power amplifiers and voltage buffers, considering them also in the fully differential version. Simulation and measurement results showing good general performance will be also presented.     

IC Voltage to Current Transducers with Very Small Transconductance

This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 m 1 level below 15 _RMS and dynamic range of 63 dB. The power consumption is only 10 watts and the supply voltages are ± 1.5 volts.     

“Square Root Domain” Filter Design and Performance

This paper discusses the implementation and performance of square root domain filters, which can be considered as the CMOS equivalent of the bipolar log domain technique. The square root design methodology is based on exploiting the MOSFET large-signal square law characteristic to implement filters which are input-output linear, but operate with internally non-linear signals. The design of subcircuits required for the implementation of square root domain filters is described based on the MOSFET translinear principle, and various performance issues are discussed. Simulation and measured results are also presented to confirm the validity of this approach, which may be attractive for low-voltage operation at frequencies in the MHz range.     

Bulk-tuned Gm–C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom׳s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35 μm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.     

A CMOS Hearing Aid Device

In this paper a CMOS Hearing Aid Device is described. The system is composed of a low-distortion low-noise preamplifier, an automatic gain control (AGC), a fully programmable switched-capacitor filter (equalizer), and a control system. The device has been fabricated in a 1.2 m CMOS analog process. The dynamic range of the device is 55 dB while the harmonic distortion components are below –50 dB. Experimental results show the feasibility of the proposed architecture.     

A 3.3 V Power Feedback Chip for Linearization of RF Power Amplifiers

The power feedback technique is a simple and low cost linearization scheme suitable for consumer products such as hand sets. This paper presents a custom chip for linearization of RF power amplifiers using power feedback. The chip, implemented in a standard double-metal double-poly 0.6 m CMOS process, operates with 3.3 V supply voltage and consumes 62 mW. When it was used to linearize a commercially available high efficiency RF power amplifier at 850 MHz, experimental results showed that out-of-band power at 30 kHz offset was reduced some 10 dB for a /4-shifted DQPSK modulated North American digital cellular (NADC) signal. For the same level of adjacent channel interference (ACI), the efficiency was increased from 35% to 48%.     

84dB动态范围13b/400kHz/3V/5.88mW ΣΔ模数转换器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器. 为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现. 电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm. 调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW. 测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

Alternative Realizations of CMOS Current Feedback Amplifiers for Low Voltage Applications

Two variants of a new current feedback amplifier (CFA) are presented in this paper. These CFAs are realized in CMOS technology and both are capable of working at low voltages. It is shown that one circuit performs better than the other by virtue of an increased impedance at its Z terminal achieved through the use of additional transistors. Analysis of both variants of the current conveyor and buffer that form the current feedback amplifier gives an insight into the location of primary poles and zeros of the CFAs. Simulation results indicate an overall gain bandwidth product in excess of 59 MHz and 102 MHz for each circuit at a gain of –10 and with a 3.3 V supply. Experimental results from a chip fabricated in a 0.35 m CMOS technology agree closely with the simulation results.     

Switched-Current Wave Filters with Reduced Number of Current Inversions

Switched-current wave filters offer very simple structures, as their main building blocks are current mirrors. On the other hand, the achieved accuracy is mainly degraded due to the effect of MOS transistor parameters mismatch. In this Letter, new configurations of serial and parallel adaptors that are used in the simulation of inductances and capacitors of the LC ladder prototype are introduced. These have been implemented using an appropriate sharing of the delay that should be presented between the incident and reflected waves at a port of adaptor, and a 3-phase clocking scheme. The number of required current inversions and consequently the effect of mismatching are reduced in the proposed configurations.     

High-Selectivity Switched-Capacitor Bandpass Filter with Quasi-Continuous Quality Factor Tunability

This paper describes the design and implementation of a second-order switched-capacitor (SC) bandpass (BP) filter with very wide quality factor (Q) programmability range. The filter selectivity is digitally programmed by varying the effective sampling frequency of an SC branch, without modifying any capacitor value. The proposed approach allows a quasi-continuous Q-factor tunability avoiding, in principle, the inherent quantization error associated to any traditional programming technique. Automatic Q-factor tuning is performed by using a scheme based on an amplitude-locking loop approach. Experimental results obtained from a 0.8-m CMOS integrated prototype demonstrate the versatility of the proposed technique for high-Q SC BP filters.     

A 0.18 μm CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s

A new transimpedance amplifier (TIA) for 2.5 Gb/s optical communications fabricated in a standard 0.18 μm CMOS process is presented. The proposed TIA is based on a conventional structure with an inverting voltage amplifier and a feedback resistor, but incorporates a new technique to enhance the input dynamic range and to prevent the TIA from saturation at high input currents. According to electrical characterization the receiver shows an optical sensitivity of −26 dB m for a BER=10⁻¹², assuming a responsivity of 1 A/W, and an optical power dynamic range above 26 dB. The power consumption of the core is only 10.6 mW at a single supply voltage of 1.8 V.     

Lumped-element analysis and design of CMOS distributed amplifiers with image impedance termination

This paper presents a systematic matrix-based lumped-element analysis of CMOS distributed amplifiers (DAs). Since transmission lines (TLs) of the DAs are artificially constructed from a ladder of a finite number of inductors and capacitors, the conventional TL-based analysis of microwave DAs can not be accurately applied to CMOS DAs. The proposed lumped-analysis method is also more intuitive for analog circuit designers than the TL analysis adapted from microwave amplifiers analysis because it provides the performance characteristics of the amplifiers as functions of circuit elements values, and not the TL characteristics. The image impedance technique is used for the design of input/output terminating networks. A new image impudence matrix is defined to accommodate the extension of the theory from two- to four-port networks, and a practical realization of the image impedance matrix is presented using the available circuit elements in CMOS technology. The simulation results clearly indicate an improved voltage gain and a better gain uniformity over the bandwidth of the proposed DA design terminated at its image impedance compared with the amplifier terminated at its nominal TL characteristics impedance.     

Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor

A compact, tunable CMOS transconductor is presented. The combined use of a Floating-Gate MOS (FGMOS) differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity. Measurement results for a prototype fabricated using a 0.8 m CMOS technology are provided, confirming on silicon the validity of the proposed approach.