A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

Low-power current-reused RF front-end based on optimized transformers topology

This paper discusses the design, analysis and performance of a 2.4 GHz fully integrated low-power current-reused receiver front-end implemented in 0.18 μm CMOS technology. The front-end is composed of a single-to-differential low-noise amplifier (LNA), using high-Q differential transformers and inductors and a coupled switching mixer stage. The mixer transconductor and LNA share the same DC current. Measurements of performance show a conversion gain of 28.5 dB, noise figure of 6.6 dB, 1 dB compression point of −32.8 dBm and IIP3 of −23.3 dBm at a 250 kHz intermediate frequency, while dissipating 1.45 mA from a 1.2 V supply.     

Wideband and multiband CMOS LNAs: State-of-the-art and future prospects

The realization of Software Defined Radio (SDR) requires flexible RF front-end to accommodate multiple standards in different frequency bands. In this review paper, we survey the literature over the period 1995–2011 and discuss the state-of-the-art multiband and wideband LNAs in context of different receiver architectures suitable for SDR. Wideband and multiband LNA designs reported in open literature are categorized on the basis of their circuit architecture. Measured results of the sample LNA designs from each category are tabulated and discussed with emphasis on power consumption, NF, gain, linearity, and impedance matching tradeoffs. We have also discussed our own three wideband inductorless LNA design prototypes which are manufactured in 0.13 µm and 90 nm CMOS. This review infers that future LNAs suitable for SDR must be highly linear and scalable with future technology nodes.     

新型差动输入CMOS电流传送器及其应用

基于P阱CMOS工艺提出了一种新的差动输入电流传送器。通过引入误差抑制负反馈电路,有效地减小了信号失真,拓宽了电路线性动态范围。文中还详细分析了电路性能,并由此指导电路的优化。给出的几个典型应用电路表明,与第二代电流传送器（CCII）相比,差动输入电流传送器的通用性更强,可获得较简洁的电路结构。本文最后设计了一个既可作为电流模式又可作为电压模式的MOSFET－C二阶滤波器。PSPICE模拟表明所提出的电路与其它同类电路相比具有更好的电路特性。     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

New 1.5-V CMOS second generation current conveyor based on wide range transconductor

This paper presents a novel CMOS low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed CCII+ uses two n-channel differential pairs instead of the complementary differential pairs; i.e. (n-channel and p-channel), to realize the input stage. This solution allows almost a rail-to-rail input and output operation; also it reduces the number of current mirrors needed in the input stage. The CCII+ is operating at supply voltages of ±0.75 V with a total standby current of 133 μA. The application of the proposed CCII+ to realize a MOS-C second order maximally flat low-pass filter is given. PSpice simulation results for the proposed CCII+ and its application are given. Ahmed H. Madian was born in Jeddah, Saudi Arabia in 1975. He received the B.Sc. degree with honors, and the M.Sc. degree in electronics and communications from Cairo University, Cairo, Egypt, in 1997, and 2001 respectively. He is currently a Research Assistant in the Electronics Engineering Department, Micro-Electronics Design Center, Egyptian Atomic Energy Authority, Cairo, Egypt. His research interests are in circuit theory; low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed/digital applications on filed programmable gate arrays. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the BSc degree with honors in 1994, the MSc degree in 1996, and the PhD degree in 1999, all from the Electronics and Communications Department, Cairo University, Egypt. He is currently an Associate Professor at the Electrical Engineering Department, Fayoum University, Egypt. He is currently also a visiting Associate Professor at the Electrical and Electronics Engineering Department, German University in Cairo, Egypt. In 2005, He was decorated with the Science Prize in Advanced Engineering Technology from the Academy of Scientific Research and technology. His research and teaching interests are in circuit theory, fully-integrated analog filters, high-frequency transconductance amplifiers, low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964,the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997-September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985-1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987-1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr Soliman gave a lecture at Nanyang Technological University, Singapore.Dr Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004-Now.     

Novel floating simulated inductors with wider operating-frequency ranges

In this paper, a number of simulated floating inductors (FIs) employing second-generation current conveyor (CCII), current-feedback operational amplifier (CFOA), differential voltage current conveyor (DVCC) and differential difference current conveyor (DDCC) are proposed. They employ only a grounded capacitor; accordingly, they are suitable for integrated circuit (IC) implementation. Some of the developed FI simulators demonstrate the feature of improved low-frequency performance while the other ones suffer from the Z/Y terminal parasitic resistors bringing extra series resistors to the inductances of the simulated FIs. Two novel methods for reducing/eliminating the unwanted series resistance in equivalent inductances of the FIs are developed, one of which is called the direct design technique accomplished by adjusting the resistive component/components of the FIs. The series resistors of the FIs affecting their low-frequency performance can be canceled by adding floating negative resistors in series, which is another method. Three of the presented FIs as examples are chosen in order to verify the developed method, perform their simulations and show their performance.     

A low power high-performance area efficient RF front-end exploiting body effect for 2.4 GHz IEEE 802.15.4 applications

The rising internet-of-things applications in home automation, smart wearables, healthcare monitoring demand small, area efficient, high-performance and low power radio frequency (RF) blocks for effective short-range communication. This growing market demand is addressed in this paper by proposing a fully CMOS radio frequency front-end (RFE) exploiting bulk effect. Apart from the primary function of frequency translation, proper circuit performance concerning the linearity, conversion gain, and noise figure is required for low-cost densely integrated transceivers operating in the 2.4 GHz ISM band. The proposed RFE at 2.4 GHz is designed and implemented in UMC 180 nm CMOS process technology with two modes of operation. In high gain mode (Mode-I), the post-layout simulation with SpectreRF shows a peak gain of 30.06 dB, IIP2 at 64.52 dBm, IIP3 at −2.74 dBm and a DSB-NF of 7.68 dB while consuming only 9.24 mW from the 1.8 V supply. In the high linear mode (Mode-II), the RFE achieves a higher IIP3 of 10.78 dBm, IIP2 of 91.56 dBm, the conversion gain of 23.5 dB, DSB-NF of 9.46 dB while consuming a low power of 3.6 mW. The fully CMOS circuit occupies a core area of only 0.0021 mm². The proposed front-end exhibits a spurious free dynamic range (SFDR) of 81.18 dB ensuring the high dynamic operation of the wireless system.     

2.4GHz0.25μmCMOS集成低噪声放大器的设计

采用TSMC 0.25mm CMOS工艺,设计了单端和差分两种工作在2.4GHz可应用于蓝牙的全集成低噪声放大器。详述了设计过程并给出了优化仿真结果。经比较得出,差分低噪声放大器为了取得和单端低噪声放大几乎同样的性能,要消耗双倍的功耗和面积,但因其对共模信号干扰的免疫力以及对衬底耦合的抑制作用而越来越受到青睐。     

工作在0.5V电压下用于无线传感网的低噪声放大器设计与优化

本文阐述了一款用于无线传感器网络可工作在0.5V电压下的低噪声放大器芯片的设计和优化方法。该芯片采用0.13 um CMOS工艺实现。本文中对其电路进行了详细分析,并提出了一种新的优化设计方法。该芯片的测试结果显示,此款低噪声放大器的功率增益为14.13dB,噪声系数最低为1.96dB,直流功耗3mW,输入1dB压缩点为-19.9dBm。S11和S22均在-10dB以下。测试结果显示此款低噪放完全适用于低电压低功耗应用。     

Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers

The linearity of two 90 nm CMOS low-noise amplifiers has been measured and analyzed. The analysis is based on Taylor series expansion of simulated I-V characteristics. The two amplifiers are cascode amplifiers with transistors of the same size but with different loads. Even though the center frequencies of the amplifiers are as high as 15 and 20 GHz, respectively, the measured results correlate well with the low-frequency-based estimation of linearity. The analysis shows that for a low load impedance, the dominating source of nonlinearity is transconductance, while for a high load impedance the nonlinearity of the output conductance instead dominates.     

A 1 V switchable CMOS LNA for 802.11A/B WLAN applications

A new dual-band, 2.4 and 5.2 GHz, combined LNA, which can operate at 1 V supply only, for WLAN application is presented. The switched transistor technique is used in the LNA. It could match the input port in two frequency bands and reduce one on-chip spiral inductor usage compared with [1, 2]. Theoretical analysis and transistor level simulation results using 0.18 μm CMOS process from Chartered Semiconductor are presented to demonstrate this idea. Wang-Chi Cheng received his B.Eng., M.Phil., and Ph.D. degrees in Electronic Engineering of the Chinese University of Hong Kong (CUHK) in 1999, 2001 and 2004. His research achievements during M.Phil. and Ph.D. studies were in the field of low voltage receiver front-end circuits design with CMOS technology. He joined the Electrical and Electronic Engineering department of Nanyang Technological University (NTU), Singapore, in May 2005 as a Research Fellow. Now, he is a Senior Engineer in charge of the UWB transceiver IC design in Hong Kong Applied Science and Technology Research Institute (ASTRI). His current research interests include 802.11 A/B WLAN and UWB transceiver design. He is also a paper reviewer of the IEEE Microwave and Wireless Components Letters. Jian-Guo Ma received his B.Sc. and M.Sc. in 1982 and 1988 respectively with honors from Lanzhou university of Chain, and Doctoral Degree in Engineering from Gerhard-Mercator University of Germany in 1996. From Jan. 1982 to March 1991, he has worked with Lanzhou university of China on RF & Microwave Engineering. Before he joined Nanyang Technological University in 1997, he was with Technical University of Nova Scotia, Canada. Now, he is a Professor of the University of Electronic Science and Technology of China. His research interests are: RFIC designs for wireless applications; RF characterization and modeling of semiconductor devices; RF interconnects and packaging; SoC and Applications; EMC/EMI in RFICs. He has published more than 150 technical papers and two books in above mentioned areas. He holds 6 patents in CMOS RFICs. He is now Associate Editor for IEEE Microwave and Wireless Components Letters. Kiat-Seng Yeo received his B.E. (Hons.) (Elect) in 1993, and Ph.D. (Elect. Eng.) in 1996 both from Nanyang Technological University, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore as a Lecturer in 1996, and became an Assistant Professor and an Associate Professor in 1999 and 2002, respectively. Professor Yeo provides consulting to statutory boards and multinational corporations in the areas of semiconductor devices and electronic circuit design. He has been extensively involved in the modeling and fabrication of small MOS/Bipolar integrated technologies for the last ten years. His research interests also include the design of new circuits and systems (based on scaled technologies) for low-voltage low-power applications; radio frequency integrated circuit (RF IC) design; integrated circuit design of BiCMOS/CMOS multiple-valued logic circuits, domino logic, and memories; and device characterization of deep submicrometer MOSFETs. Manh-Anh Do obtained his B.E. (Hons) (Elect.) in 1973, and Ph.D. (Elect. Eng.) in 1977 both from University of Canterbury, New Zealand. Between 1977 and 1989, he held various positions including: R & D engineer and production manager at Radio Engineering Ltd., research scientist at Fisheries Research Centre, New Zealand, and senior lecturer at National University of Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore as a senior lecturer in 1989, and obtained the Associate Professorship in 1996 and the Professorship in 2001. He has been a consultant for many projects in the Singapore electronic industry, and was the principal consultant for the design, testing and implementation of the $200 million Electronic Road Pricing (ERP) island-wide project in Singapore, from 1990 to 2001. His current research is on digital and mobile communications, RF IC design, mixed-signal circuits and intelligent transport systems. Before that, he specialsed in sonar designing, biomedical engineering and signal processing. Since 1995, he has been Head of Division of Circuits and Systems, School of EEE, NTU. He is a Fellow of IEE, UK, a Chartered Engineer (UK) and a Professional Engineer (Singapore).     

一种基于OFDM UWB接收机的CMOS下变频混频器

设计了基于正交频分复用(OFDM)超宽带(UWB)系统的下变频混频器(Mixer),并采用0.18μm RF CMOS工艺,通过一种不同于传统Gilbert结构的新颖的双平衡结构来实现,以降低本振大信号对输出中频端的噪声贡献和干扰,降低混频器的静态直流功耗等.测试结果表明:在4～252MHz的中频范围内,转换增益大于2.5～7.8dB,线性度IIP3大于3.3dBm,噪声系数为22.5～26dB,各端口间隔离度均在约-50dB,在1.8V电压下消耗总电流约为8mA.