Polymer nanocomposite dielectric based on P(VDF-TrFE)/PMMA/BaTiO3 for TIPs-pentacene OFETs

TIPs-pentacene OFETs were fabricated on a plastic substrate using polymer nanocomposite dielectric. The blend polymer P(VDF-TrFE)/PMMA (30 wt%) was used as polymer matrix and BaTiO₃ nanoparticles modified by 3-glycidoxypropyltrimethoxysilane (GPTMS) were dispersed as ceramic fillers. The effects of different loadings of BaTiO₃ on the surface morphology and electrical properties of dielectric films were investigated. The formulation of screen-printable dielectric ink of P(VDF-TrFE)/PMMA/BaTiO₃/Silica (SII) was achieved by adding fumed silica as the viscosity modifier. TIPs-pentacene OFETs using SII as the gate dielectric features a mobility of 0.01 cm²/V s, and having a threshold voltage of −6 V. This screen-printable dielectric ink is promising for low operating-voltage fully-printed OFETs.     

1 Volt organic transistors with mixed self-assembled monolayer/Al2O3 gate dielectrics

Control of the threshold voltage and the subthreshold swing is critical for low voltage transistor operation. In this contribution, organic field-effect transistors (OFETs) operating at 1 V using ultra-thin (∼4 nm), self-assembled monolayer (SAM) modified aluminium oxide layers as the gate dielectric are demonstrated. A solution-processed donor–acceptor semiconducting polymer poly(3,6-di(2-thien-5-yl)-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione)thieno[3,2-b]thiophene) (PDPP2TTT) is used as the active layer. It is shown that the threshold voltage of the fabricated transistors can be simply tuned by carefully controlling the composition of the applied SAM. The optimised OFETs display threshold voltages around 0 V, low subthreshold slopes (150 ± 5 mV/dec), operate with negligible hysteresis and show average saturated field-effect mobilities in excess of 0.1 cm²/V s at 1 V.     

High performance inkjet-printed C60 fullerene thin-film transistors: Toward a low-cost and reproducible solution process

We have demonstrated high performance inkjet-printed n-channel thin-film transistors (TFTs) using C₆₀ fullerene as a channel material. Highly uniform amorphous C₆₀ thin-film patterns were fabricated on a solution-wettable polymer gate dielectric layer by inkjet-printing and vacuum drying process. Fabricated C₆₀ TFTs shows great reproducibility and high performance; field-effect mobilities of 2.2–2.4 cm² V^?1 s^?1, threshold voltages of 0.4–0.6 V, subthreshold slopes of 0.11–0.16 V dec^?1 and current on/off ratio of 10⁷–10⁸ in a driving voltage of 5 V. This is due to the efficient annealing process that extracting the solvent residue and the formation of low trap-density gate dielectric surface.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Vacuum-processed polyethylene as a dielectric for low operating voltage organic field effect transistors

We report on the fabrication and performance of vacuum-processed organic field effect transistors utilizing evaporated low-density polyethylene (LD-PE) as a dielectric layer. With C₆₀ as the organic semiconductor, we demonstrate low operating voltage transistors with field effect mobilities in excess of 4 cm²/Vs. Devices with pentacene showed a mobility of 0.16 cm²/Vs. Devices using tyrian Purple as semiconductor show low-voltage ambipolar operation with equal electron and hole mobilities of ～0.3 cm²/Vs. These devices demonstrate low hysteresis and operational stability over at least several months. Grazing-angle infrared spectroscopy of evaporated thin films shows that the structure of the polyethylene is similar to solution-cast films. We report also on the morphological and dielectric properties of these films. Our experiments demonstrate that polyethylene is a stable dielectric supporting both hole and electron channels.     

Integration of a graphene ink as gate electrode for printed organic complementary thin-film transistors

We demonstrate a new electrode gate based on graphene ink for complementary printed organic metal oxide semiconductor (CMOS) technology on flexible plastic substrates. The goal is to replace the standard silver electrode gate. Devices made with graphene were enhanced and showed a high field-effect mobility of 3 cm² V⁻¹ s⁻¹ for P-type and 0.9 cm² V⁻¹ s⁻¹ for the N-type semiconductors. The improvement is attributed to the increase of the electrical capacitance of the organic dielectric (CYTOP) due to the graphene layer. A seven-stage ring oscillator was made with high oscillation frequencies of 2.1 kHz at 40 V corresponding to a delay/gate value of 34 μs. These performances are promising for use of low cost printed electronic applications.     

Complementary-like inverters based on an ambipolar solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative

We report on high-mobility top-gate organic field-effect transistors (OFETs) and complementary-like inverters fabricated with a solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative as the channel semiconductor and a CYTOP/Al₂O₃ bilayer as the gate dielectric. The OFETs showed ambipolar behavior with average electron and hole mobility values of 1.2 and 0.01 cm² V^?1 s^?1, respectively. Complementary-like inverters fabricated with two ambipolar OFETs showed hysteresis-free voltage transfer characteristics with negligible variations of switching threshold voltages and yielded very high DC gain values of more than 90 V/V (up to 122 V/V) at a supply voltage of 25 V.     

Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics

A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO₂ nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the I–V curve, a threshold voltage (V_T) of 2.2 V, a field-effect mobility on the order of 0.1 cm²/V s and an I_ON/I_OFF ratio of about 10⁴. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

High mobility and low operation voltage organic field effect transistors by using polymer-gel dielectric and molecular doping

In this work, we present a method to increase the performance in solution processed organic field effect transistors (OFET) by using gel as dielectric and molecular doping to the active organic semiconductor. In order to compare the performance improvement, Poly (methylmethacrylate) (PMMA) and Poly (3-hexylthiophene-2,5-diyl) P3HT material system were used as a reference. Propylene carbonate (PC) is introduced into PMMA to form the gel for using as gate dielectric. The mobility increases from 5.72×10⁻³ to 0.26 cm² V s^–1 and operation voltage decreases from −60 to −0.8 with gel dielectric. Then, the molecular dopant 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ) is introduced into P3HT via co-solution. The mobility increases up to 1.1 cm² V s^–1 and the threshold voltage downs to −0.09 V with doping. The increase in performance is discussed in terms of better charge inducing by high dielectric properties of gel and trap filling due to the increased carrier density in active semiconductor by molecular doping.     

Natural polyelectrolyte: Major ampullate spider silk for electrolyte organic field-effect transistors

The major ampullate (MA) silk collected from giant wood spiders Nephila pilipes consists of 12% glutamic acid (Glu) and 4% tyrosine (Tyr) acidic amino residues. The MA silk may act as a natural polyelectrolyte for organic field-effect transistors (OFETs). Pentacene and F₁₆CuPc OFETs were fabricated with the MA silk thin film as the gate dielectric. The MA silk thin film with surface roughness of 4 nm and surface energy of 36.1 mJ/m² was formed on glass using a hexafluoroisopropanol (HFIP) organic process. The MA silk gate dielectric in pentacene OFETs may improve the field-effect mobility (μ_FE,sat) value in the saturation regime from 0.11 in vacuum to 4.3 cm² V⁻¹ s⁻¹ in air ambient at ca. 70% RH. The corresponding threshold voltage (V_TH) value reduced from −6 V in vacuum to −0.5 V in air ambient. Similar to other polyelectrolytes, the changes of μ_FE,sat and V_TH may be explained by the generation of electric double layers (EDLs) in the MA silk thin film in air ambient due to water absorption.     

The role of water in the device performance of n-type PTCDI-C8 organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C₈) organic field-effect transistors (OFETs). An aqueous solution process was applied to form the gelatin gate dielectric on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. The field-effect mobility in the saturation regime (μ_FE,sat) and the threshold voltage (V_T) values of a typical 40 nm PTCDI-C₈ OFET are (0.22 cm² V⁻¹ s⁻¹, 55 V) in vacuum and (0.74 cm² V⁻¹ s⁻¹, 2.6 V) in air ambient. The maximum voltage shift in hysteresis is also reduced from 10 V to 2 V when the operation environment for PTCDI-C₈ OFETs is changed from vacuum to air ambient. Nevertheless, a slight reduction of electron mobility was found when the device was stressed in the air ambient. The change in the device performance has been attributed to the charged ions generation owing to water absorption in gelatin in air ambient.     

Light-emitting field-effect transistors with π-conjugated liquid crystalline polymer driven by AC-gate voltages

Light-emitting field-effect transistors with a liquid crystalline polymer of poly[(9,9-dioctylfluorenyl-2,7-diyl)-co-bithiophene] (F8T2) were investigated under alternating current (AC) gate operations. Bottom-contact/top-gate devices were fabricated with indium-tin-oxide (ITO) source/drain electrodes, a poly(methyl methacrylate) dielectric and a gold gate electrode. The crystalline F8T2 film exhibited ambipolar characteristics with electron and hole mobilities of 1.8 × 10^?3 and 2.5 × 10^?3 cm²/V s, respectively, although the threshold voltage was considerably higher for electron injection. By applying square-wave voltages to the gate, light emission was obtained at the both edges of the source and drain electrodes by alternating injection of opposite carriers even when the source and drain were grounded. The light intensity was enhanced in the channel region by biasing the source negative while biasing the drain positive where the holes injected from the drain were transported to recombine with the electrons injected at the source edge.     

Flexible high mobility pentacene transistor with high-k/low-k double polymer dielectric layer operating at −5 V

We report on the fabrication of pentacene-based thin-film transistors (TFTs) with a 230 nm-thick double polymer dielectric composed of 30 nm-thin low-k poly-4-vinyphenol (PVP) and 200 nm-thick high-k poly(vinylidene fluoride/trifluoroethylene) [P(VDF–TrFE)] dielectric on polyethersulfone (PES) films. Our 230 nm-thick double (high-k/low-k) polymer showed a good dielectric strength of ～2 MV/cm, a high capacitance of 26 nF/cm² with k = ～7. Based on this double polymer dielectric, our flexible pentacene TFT displayed a high saturation mobility of 1.22 cm²/V s, a threshold voltage of ?2.5 V, and on/off ratio of 10³, stably operating under ?5 V.     

Solution-processed single-crystalline organic transistors on patterned ultrathin gate insulators

Single-crystalline organic transistors of 3,11-didecyl-dinaphtho[2,3-d:2′,3′-d′]benzo[1,2-b:4,5-b′]dithiophene (C₁₀-DNBDT-NW) and 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C₁₀-DNTT) were fabricated by solution processes on top of the patterned hybrid ultrathin gate dielectrics consisting of 3.6 nm-thick aluminum oxide and self-assembled monolayers (SAMs). Due to the excellent crystallinity of the channel films, bottom-gate and top-contact field-effect transistors exhibited the average field-effect mobility of 3.7 cm²/V s and 4.3 cm²/V s for C₁₀-DNBDT-NW and C₁₀-DNTT, respectively. These are the first successful devices of solution-processed single-crystalline transistors on ultrathin gate dielectrics with the mobility above 1 cm²/V s, opening the way to develop low-power-consumption and high-performance printed circuits.     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

Low power flexible organic thin film transistors with amorphous Ba0.7Sr0.3TiO3 gate dielectric grown by pulsed laser deposition at low temperature

We deposited amorphous Ba_0.7Sr_0.3TiO₃ (BST) on silicon and plastic substrate under 110 °C by pulsed laser deposition (PLD) and use it as the dielectric of the organic transistor. Depends on the thickness of BST layer, the highest mobility of the devices can achieve 1.24 cm² V^?1 s^?1 and 1.01 cm² V^?1 s^?1 on the silicon and polyethylene naphthalate (PEN) substrate, respectively. We also studied the upward and downward bending tests on the transistors and the dielectric thin films. We found that the BST dielectric pentacene transistor can maintain the mobility at 0.5 cm² V^?1 s^?1 or higher while the bending radius is around 3 mm in both upward and downward bending. Our finding demonstrates the potential application of PLD growth high-k dielectric in the large area organic electronics devices.     

Low-operating-voltage polymeric transistor with solution-processed low-k polymer/high-k metal-oxide bilayer insulators

We have successfully demonstrated a polymeric semiconductor-based transistor with low-k polymer/high-k metal-oxide (TiO₂) bilayer as gate dielectric. The TiO₂ layers are readily processable from solution and cured at low temperature, instead of traditionally sputtering or high temperature sintering process, thus may suitable for a low-cost organic field effect transistors (FETs) manufacture. The low-k polymer capped on TiO₂ layer could further smooth the TiO₂ dielectric surface and suppress the leakage current from grain boundary of TiO₂ films. The resulting unpatented P3HT-OFETs could operate with supply voltage less than 10 V and the mobility and threshold voltage were 0.0140 cm²/V s and 1.14 V, respectively. The on/off ratio was 1.0 × 10³.     

Inkjet-printed copper electrodes using photonic sintering and their application to organic thin-film transistors

We report on copper (Cu) electrodes fabricated with inkjet-printed nanoparticle inks that are photonic sintered on a polymer dielectric layer and their application to source and drain electrodes in organic thin-film transistor (TFT). By using photonic sintering with a radiant energy density of 9 J/cm², printed Cu nanoparticle layers on a glass substrate showed very low electrical resistivity levels of 7 μΩ cm. By optimizing the sintering conditions on polymer dielectric, the pentacene-based TFT using these printed Cu electrodes showed good mobility levels of 0.13 cm²/Vs and high on/off current ratios of about 10⁶. In addition, we revealed that the crystal grain growth of pentacene near the printed Cu electrodes was inhibited by the thermal damage of polymer underlayer due to the high radiant energy density of the intense light.     

A cross-linked poly(methyl methacrylate) gate dielectric by ion-beam irradiation for organic thin-film transistors

The electrical characteristics of pentacene organic thin-film transistors (OTFTs) using cross-linked poly(methyl methacrylate) (PMMA) as the gate dielectric are reported. Ultra-thin films of cross-linked PMMA could be obtained by spin-coating and subsequent irradiation using a 1.515 MeV ⁴He⁺ ion beam. The resulting film, with a thickness of 33 nm, possessed a low leakage current density of about 10^?6 A cm^?2 for fields up to 2 MV cm^?1. OTFTs incorporating the cross-linked dielectric operated at relatively low voltages, <10 V, and exhibited a mobility of 1.1 cm² V^?1 s^?1, a threshold voltage of ?1 V, a sub-threshold slope of 220 mV per decade and an on/off current ratio of 1.0 × 10⁶.