Influence of I/O oxide process on the NBTI performance of 28 nm HfO2-based HKMG p-MOSFETs

The NBTI (negative bias temperature instability) performance of 28 nm HfO₂-based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory

In this work, the origin of the anomalous tail bits have been examined thoroughly on 43 nm nitride based charge trap flash memory devices. Tunnel oxide nitridation was implemented on the device under study to enhance its immunity to charge loss mechanism. Due to the extensive program/erase cycling, the increment in the defect density in tunnel oxide layer has generated significant tail bits that exhibited detrimental charge loss at room temperature. The findings have indicated that these tail bits are attributed to randomly distributed defects due to extensive program/erase cycling stress. Furthermore, these tail bits enhanced with longer storage duration at room temperature but deterred at high storage temperature. In this work, the anomalous tail bits were suppressed at high storage temperature. The underlying physical mechanism for these anomalous tail bits was found to be attributed to trap-assisted-tunneling mechanism that enables trapped charges from nitride storage layer to leak out along the vertical path of oxide–nitride–oxide stack of nitrided flash memory. These findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be addressed to achieve desired reliability performance. This work also demonstrated that room temperature storage test is a critical test to investigate the generation of the detrimental anomalous tail bits in reliability characterization and qualification for future nitrided flash memory.     

Effect of H2 content on reliability of ultrathin in-situsteam generated (ISSG) SiO2

This letter demonstrates the effect of H₂ percentage during oxidation on the quality of the in-situ steam generated (ISSG) oxide. Our results indicate the reliability of ISSG oxide is considerably improved as the H₂ percentage increases, from the viewpoint of stress-induced leakage current (SILC) and charge-to-breakdown (Q_BD). Such enhanced reliability of the ISSG oxide may be explained by the reduction of defects in the SiO₂ network within the structural transition layer, such as Si dangling bonds, weak Si-Si and strained Si-O bonds, by highly reactive oxygen atoms which are hypothesized to be dissociated from the molecular oxygen due to the presence of hydrogen     

A 90-ns one-million erase/program cycle 1-Mbit flash memory

Describes the design and performance of a 245-mil/sup 2/ 1-Mbit (128K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.0- mu m EPROM-base technology, the 15.2- mu m/sup 2/ single-transistor EPROM tunnel oxide (ETOX) cell requires only 42 percent of the area required by the previous 1.5- mu m device. One of the most significant aspects of this 1-Mbit flash memory is the one-million erase/program cycle capability. The 1-Mbit memory exhibits 90-ns read access time while the reprogramming performance gives a 900-ms array erase time and a 10- mu s/byte programming rate. Ample erase and program margins through one-million erase/program cycles are guaranteed by the internal verify circuits. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses.<>     

Effects of erase source bias on Flash EPROM device reliability

This paper is concerned with the effects of the source bias during the erase operation on the reliability of Flash EPROM devices. It will be shown that positive charge in the tunnel oxide, mostly generated by the erase operation, is a major cause of the unintentional charge loss/gain mechanisms that disturb the data content of the memory cell. The effects of the erase source bias are evaluated in the context of the positive oxide charge generation and the resulting enhancement of the gate current that causes the data loss. An optimal source bias during erase, around 2 V for our samples, is shown to cause the least positive oxide charge. A model based on the band-to-band tunneling-induced hole generation in Si and subsequent hole injection during the erase operation is presented and discussed     

Comprehensive study on a novel bidirectional tunnelingprogram/erase NOR-type (BiNOR) 3-D flash memory cell

In this paper a recently proposed bidirectional tunneling program/erase (P/E) NOR-type (BiNOR) flash memory is extensively investigated. With the designated localized p-well structure, uniform Fowler-Nordheim (FN) tunneling is first fulfilled for both program and erase operations in NOR-type array architecture to facilitate low power applications. The BiNOR flash memory guarantees excellent tunnel oxide reliability and is provided with fast random access capability. Furthermore, a three-dimensional (3D) current path in addition to the conventional two-dimensional (2D) conduction is proven to improve the read performance. The BiNOR flash memory is thus promising for low-power, high-speed, and high-reliability nonvolatile memory applications     

SiO2隧穿层不同气氛氮化退火对MONOS存储器性能的改善

Metal–oxide–nitride–oxide–silicon(MONOS)capacitorswiththermallygrownSiO2asthetunnellayer arefabricated,andtheeffectsofdifferentambientnitridation(NH3,NOandN2O)onthecharacteristicsofthememory capacitors are investigated.The experimental results indicate that the device with tunnel oxide annealed in NO ambient exhibits excellent memory characteristics,i.e.a large memory window,high program/erase speed,and good endurance and retention performance(the charge loss rate is 14.5%after 10 years).The mechanism involved isthatmuchmorenitrogenisincorporatedintothetunneloxideduringNOannealing,resultinginalowertunneling barrier height and smaller interface state density.Thus,there is a higher tunneling rate under a high electric field and a lower probability of trap-assisted tunneling during retention,as compared to N2O annealing.Furthermore,compared with the NH3-annealed device,no weak Si–H bonds and electron traps related to the hydrogen are introduced for the NO-annealed devices,giving a high-quality and high-reliability SiON tunneling layer and SiON/Si interface due to the suitable nitridation and oxidation roles of NO.     

Stress-induced leakage current of tunnel oxide derived from flashmemory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (ΔV_th) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125°C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30°C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Characterization of thin textured tunnel oxide prepared by thermaloxidation of thin polysilicon film on silicon

In this paper, the characteristics of thin textured tunnel oxide prepared by thermal oxidation of thin polysilicon film on Si substrate (TOPS) are studied. Because of the rapid diffusion of oxygen through the grain boundaries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at the grain boundaries, the oxidation rate of the TOPS sample is close to that of a normal oxide grown on a (111) Si substrate. Also, a textured Si/SiO₂ interface is obtained. The textured Si/SiO₂ interface results in localized high fields and causes a much higher electron injection rate. The optimum TOPS sample can be obtained by properly oxidizing the stacked α-Si film, independent of the substrate doping level. Also, the optimum TOPS sample exhibits a smaller electron trapping rate and a lower interface state generation rate when compared to the sample from a standard tunnel oxide process. These differences are attributed to a lower bulk electric field and a smaller injection area in the TOPS samples     

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH₃ atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current     

An investigation of erase-mode dependent hole trapping in flashEEPROM memory cell

Hot-hole generation during electrical erase in flash memory cells was investigated and found to be strongly dependent on the lateral electric field of the gated diode junction. It is shown, by erasing the memory cell at a low source voltage in combination with a negative gate voltage, that the operating point can be chosen well away from the onset of avalanche. Using this erasing scheme appreciably reduces the amount of hole trapping in the tunnel oxide. As a result, data retention is significantly improved as compared with conventional erasure     

ISSG及其氮化工艺对NBTI效应的改善

本文在对ISSG工艺特性简单分析的基础上讨论了ISSG氧化物薄膜的可靠性问题。讨论了ISSG工艺及其相关的氮化工艺对NBTI的改善原理。数据表明ISSG工艺及其相关的氮化工艺对NBTI效应有明显的改善作用。由于原子氧的强氧化作用,ISSG工艺中最终得到的氧化物薄膜体内缺陷少,界面态密度也比较小,氧化物薄膜的质量比较高。ISSG氮化工艺与传统炉管氧化物薄膜的氮化工艺的主要区别在于N所集中的位置不一样。ISSG工艺氮化是把等离子态的N^＋注入到多晶硅栅和SiQ2的界面,不会增加SiQ2和Si衬底的界面态,从而可以显著改善NBTI效应。而传统炉管氧化物薄膜的氮化是用NO或者N2O把N注入到SiQ2和Si衬底的界面,这样SiQ2和Si的界面态就会增加,从而增强NBTI效应。     

In situ steam generation (ISSG) versus standard steam technology: impact on oxide reliability

This work studies the reliability behaviour of gate oxides grown by in situ steam generation technology. A comparison with standard steam oxides is performed, investigating interface and bulk properties. A reduced conduction at low fields and an improved reliability is found for ISSG oxide. The initial lower bulk trapping, but with similar degradation rate with respect to standard oxides, explains the improved reliability results.     

基于原位水汽生成工艺的栅氧化膜特性

介绍了一种制作栅介质的新工艺--原位水汽生成工艺.基于Deal-Grove模型提出了原位水汽生成过程中活性氧原子和硅一硅键反应形成硅氧硅键的氧化模型,并通过MOS电容结构对原位水汽生成和炉管湿法氧化所形成的栅氧化膜的电击穿特性进行了研究和分析.测试结果表明原位水汽生成的栅氧化膜相对于炉管湿法氧化有着更为突出的电学性能,这可以认为是由于弱硅一硅键的充分氧化所导致的.表明原位水汽生成在深亚微米集成电路器件制造中具有广阔应用前景.     

Novel N2O-oxynitridation technology for forming highlyreliable EEPROM tunnel oxide films

Ultrathin (≃6 nm) oxynitrided SiO₂ (SiO_xN_y) films have been formed on Si(100) by rapid thermal processing (RTP) in an N₂O ambient. It is demonstrated that with this technology the generation of electron traps in bulk SiO₂ and the low-field leakage during Fowler-Nordheim electron injection can be greatly reduced. This behavior of SiO_x N_y film can be explained by the idea that the trap sites are reduced by forming strong Si-N bonds in bulk SiO₂. This N₂O oxynitridation is viewed as a hopeful technology for forming ultrathin EEPROM tunnel oxide films     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.