A cross-linked poly(methyl methacrylate) gate dielectric by ion-beam irradiation for organic thin-film transistors

The electrical characteristics of pentacene organic thin-film transistors (OTFTs) using cross-linked poly(methyl methacrylate) (PMMA) as the gate dielectric are reported. Ultra-thin films of cross-linked PMMA could be obtained by spin-coating and subsequent irradiation using a 1.515 MeV ⁴He⁺ ion beam. The resulting film, with a thickness of 33 nm, possessed a low leakage current density of about 10^?6 A cm^?2 for fields up to 2 MV cm^?1. OTFTs incorporating the cross-linked dielectric operated at relatively low voltages, <10 V, and exhibited a mobility of 1.1 cm² V^?1 s^?1, a threshold voltage of ?1 V, a sub-threshold slope of 220 mV per decade and an on/off current ratio of 1.0 × 10⁶.     

4H–SiC BJTs with current gain of 110

4H–SiC BJTs with a common emitter current gain of 110 have been demonstrated. The high current gain was attributed to a thin base of 0.25 μm which reduces the carrier recombination in the base region. The device open base breakdown voltage (BV_CEO) of 270 V was much less than the open emitter breakdown voltage (BV_CBO) of 1560 V due to the emitter leakage current multiplication from the high current gain by “transistor action” of BJTs. The device has shown minimal gain degradation after electrical stress at high current density of >200 A/cm²up to 25 h.     

On the current conduction mechanisms of CeO2/La2O3 stacked gate dielectric

It was found that the electrical properties of CeO₂/La₂O₃ stack are much better than a single layer La₂O₃ film. A thin CeO₂ capping layer can effectively suppress the oxygen vacancy formation in the La₂O₃ film. This work further investigates the current conduction mechanisms of the CeO₂ (1 nm thick)/La₂O₃ (4 nm thick) stack. Results show that this thin stacked dielectric film still has a large leakage current density; the typical 1−V leakage can exceed 1 mA/cm² at room temperature. The large leakage current should be due to both the oxide defect centers as well as the film structure. Results show that at low electric field (<0.2 MV/cm), the thermionic emission induced current conduction in this stacked structure is quite pronounced as a result of interface barrier lowering due to the capping CeO₂ film which has a higher k value than that of the La₂O₃ film. At higher electric fields, the current conduction is governed by Poole–Frenkel (PF) emission via defect centers with an effective energy level of 0.119 eV. The temperature dependent current–voltage characteristics further indicate that the dielectric defects may be regenerated as a result of the change of the thermal equilibrium of the redox reaction in CeO₂ film at high temperature and the drift of oxygen under the applied electric field.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Border traps and bias-temperature instabilities in MOS devices

An overview of the effects of border traps on device performance and reliability is presented for Si, Ge, SiGe, InGaAs, SiC, GaN, and carbon-based MOS devices that are subjected to bias-temperature stress, with or without exposure to ionizing radiation. Effective border-trap densities and/or energy distributions are estimated using capacitance-voltage hysteresis, low-frequency noise, charge pumping, and other electrical techniques that vary the time scale over which charge exchange between the semiconductor channel and near-interfacial dielectric. Oxygen vacancies and hydrogen impurity complexes are common border traps in a wide variety of systems subjected to bias-temperature stress. Charge trapping and emission tend to dominate observed bias-temperature instabilities for as-processed devices at higher oxide electric fields (> 4–6 MV/cm), and for irradiated devices. Hydrogen diffusion and reactions become relatively more significant in as-processed devices at lower electric fields (< 4–6 MV/cm).     

Structural,optical and dielectric properties of HfSiO films prepared by co-evaporation method

HfSiO dielectric films were prepared on Si substrate by the co-evaporation method. The chemical composition, crystalline temperature, optical and electrical properties of the compound film were investigated. X-ray photoelectron spectroscopy analysis illustrated that the atom ratio of Hf to Si was about 4:1 and Hf–Si–O bonds appeared in the film. The X-ray diffraction analysis revealed that the crystalline temperature of the film was higher than 850 °C. Optical measurements showed that the refractive index was 1.82 at 550 nm wavelengths and the optical band gap was about 5.88 eV. Electrical measurements demonstrated that the dielectric constant and a fixed charge density were 18.1 and 1.95×10¹² cm⁻² respectively. In addition, an improved leakage current of 7.81 μA/cm² at the gate bias of −3 V was achieved for the annealed HfSiO film.     

Organic field-effect transistors based on low-temperature processable transparent polymer dielectrics with low leakage current

A solution-based transparent polymer was investigated as the gate dielectric for organic field-effect transistors (OFETs). Organic thin films (400 nm) are readily fabricated by spin-coating a polyhydrazide solution under ambient conditions on the ITO substrates, followed by annealing at a low temperature (120 °C). The smooth transparent dielectrics exhibited excellent insulating properties with very low leakage current densities of ～10^?8 A/cm². High performance OFETs with evaporated pentacene as organic semiconductor function at a low operate voltage (?15 V). The mobility could reach as high as 0.7 cm²/Vs and on/off current ratio up to 10⁴. Solution-processed TIPS-pentacene OFETs also work well with this polymer dielectric.     

High performance sol–gel spin-coated titanium dioxide dielectric based MOS structures

High-κ TiO₂ thin films have been fabricated using cost effective sol–gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO₂ films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 °C, retaining its structural integrity up to 1000 °C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance–voltage (C–V) characteristics of the films annealed at 400 °C exhibited a high value of dielectric constant (~34). Further, frequency dependent C–V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO₂/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent ‘s’=0.85). A low leakage current density of 3.6×10⁻⁷ A/cm² at 1 V was observed for the films annealed at 600 °C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-κ materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and ALD. The results also suggest that the high value of dielectric constant ‘κ‘ obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Amorphous ternary rare-earth gate oxides for future integration in MOSFETs

In this contribution we present results on the structural and electrical properties of amorphous REScO₃ (RE = La, Gd, Tb, Sm) and LaLuO₃ thin films. The study reveals that these oxides are potential candidates for so-called higher-k dielectrics for forthcoming MOSFET generations. High dielectric constants up to 32, low leakage currents and low interface trap densities are determined for amorphous thin films prepared by pulsed-laser deposition, molecular beam deposition and e-gun evaporation. Moreover, we show that LaLuO₃ gate stacks annealed up to 1050 °C maintain low leakage current densities without substantial EOT increase. Finally, promising results for n-MOSFETs with GdScO₃ as gate dielectric processed on strained silicon-on-insulator substrates are also shown.     

High dielectric constant TiO2 film grown on polysilicon by liquid phase deposition

In this study, titanium dioxide (TiO₂) films were grown on polycrystalline silicon by liquid phase deposition (LPD) with ammonium hexafluoro-titanate and boric acid as sources. The film structure is amorphous as examined by X-ray diffraction (XRD). A uniform composition of LPD-TiO₂ was observed by SIMS examination. The leakage current density of an Al/LPD-TiO₂/poly-Si/p-type Si metal–oxide–semiconductor (MOS) structure is 1.9 A/cm² at the negative electric field of 0.7 MV/cm. The dielectric constant is 29.5 after O₂ annealing at 450 °C. The leakage current densities can be improved effectively with a thermal oxidized SiO₂ added at the interface of LPD-TiO₂/poly-Si. The leakage current density can reach 3.1×10⁻⁴ A/cm² at the negative electric field of 0.7 MV/cm and the dielectric constant is 9.8.     

Constant current stress of lightly Al-doped Ta2O5

The response of lightly Al-doped Ta₂O₅ stacked films (6 nm) to constant current stress (CCS) under gate injection (current stress in the range of 1 to 30 mA/cm² and stressing time of 50–400 s) has been investigated. The stress creates positive oxide charge, which is assigned to oxygen vacancies but it does not affect the dielectric constant of the films. The most sensitive parameter to the stress is the leakage current. Different degradation mechanisms control the stress-induced leakage current (SILC) in dependence on both the stress conditions and the applied measurement voltage. The origin of SILC is not the same as that in pure and Ti- or Hf-containing Ta₂O₅. The well known charge trapping in pre-existing traps operates only at low level stress resulting in small SILC at accumulation. The new trap generation plays a key role in the SILC degradation and is the dominant mechanism controlling the SILC in lightly Al-doped Ta₂O₅ layers.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

TiSiOx gate dielectrics produced by reactive sputtering for high performance InGaZnO thin film transistors

High dielectric constant TiSiOx thin films are produced by reactive sputtering under different oxygen partial pressure ratio (P_O2) from 15% to 30%. All the TiSiOx films show an excellent transmittance value of almost 95%. The TiSiOx film has a low leakage current density by optimizing oxygen partial pressure, and the leakage current density of TiSiOx film under P_O2 of 20% is 4.88×10⁻⁷ A/cm² at electrical field strength of 2 MV/cm. Meanwhile, their associated InGaZnO thin-film transistors (IGZO-TFTs) with different P_O2 TiSiOx thin films as gate insulators are fabricated. IGZO-TFTs under P_O2 of 20% shows an optimized electrical performance, and the threshold voltage, sub-threshold swing, field effect mobility and I_on/I_off ratio of this device are 2.22 V, 0.33 V/decade, 29.3 cm²/V s and 5.03×10⁷, respectively. Moreover, the density of states (DOS) is calculated by temperature-dependent field-effect measurement. The enhancements of electrical performance and temperature stability are attributed to better active/insulator interface and smaller DOS.     

Solution processable bilayered gate dielectric towards flexible organic thin film transistors

In this study, we have successfully explored the potential of a new bilayer gate dielectric material, composed of Polystyrene (PS), Pluronic P123 Block Copolymer Surfactant (P123) composite thin film and Polyacrylonitrile (PAN) through fabrication of metal insulator metal (MIM) capacitor devices and organic thin film transistors (OTFTs). The conditions for fabrication of PAN and PS-P123 as a bilayer dielectric material are optimized before employing it further as a gate dielectric in OTFTs. Simple solution processable techniques are applied to deposit PAN and PS-P123 as a bilayer dielectric layer on Polyimide (PI) substrates. Contact angle study is further performed to explore the surface property of this bilayer polymer gate dielectric material. This new bilayer dielectric having a k value of 3.7 intermediate to that of PS-P123 composite thin film dielectric (k ∼ 2.8) and PAN dielectric (k ∼ 5.5) has successfully acted as a buffer layer by preventing the direct contact between the organic semiconducting layer and high k PAN dielectric. The OTFT devices based on α,ω-dihexylquaterthiophene (DH4T) incorporated with this bilayer dielectric, has demonstrated a hole mobility of 1.37 × 10⁻² and on/off current ratio of 10³ which is one of the good values as reported before. Several bending conditions are applied, to explore the charge carrier hopping mechanism involved in deterioration of electrical properties of these OTFTs. Additionally, the electrical performance of OTFTs, which are exposed to open atmosphere for five days, can be interestingly recovered by means of re-baking them respectively at 90 °C.     

Development and application of the Oxide Stress Separation technique for the measurement of ONO leakage currents at low electric fields in 40 nm floating gate embedded-flash memory

The silicon dioxide/silicon nitride/silicon dioxide (ONO) inter-gate dielectric layer has long been used in floating gate flash memories to provide coupling with the control gate, while simultaneously blocking leakage to it. Given the thickness and quality of the ONO, it is not possible to directly measure the leakage currents at low electric fields. This article presents the Oxide Stress Separation (OSS) technique which places a flash cell in a condition where the potential drop occurs entirely across the ONO. This allows for the measurement of currents on the order of 10^− 23 A to be measured at low electric fields using nominal floating gate flash memory cells. Using OSS, state-of-the-art 40 nm embedded-flash memories are characterized, allowing an evaluation of data retention contributors. Comparing OSS results with bake tests, ONO is found to be minimally responsible for the data retention drift, even in modern memories.     

Gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices by suitable HfAlO/HfON thickness and sintering temperature

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfAlO/HfON stacks and sintering temperatures are investigated in this work. The suppression of gate leakage current and improvement of reliability properties can be achieved by either stacked gate dielectrics or a low sintering temperature. Especially, the qualities of the interface and high-k gate dielectric in Ge devices are significantly improved through a low sintering temperature. A 0.5 nm HfAlO/2.5 nm HfON gate stack and a sintering temperature at 350 °C are the suitable conditions to achieve low EOT, gate leakage, and good reliability for Ge MOS devices.     

Low-voltage organic ferroelectric field effect transistors using Langmuir–Schaefer films of poly(vinylidene fluoride-trifluororethylene)

Langmuir–Schaefer transfer was used to fabricate ultrathin films of ferroelectric copolymer, poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%), for non-volatile memory application at low operating voltage. Increasing the number of transferred monolayers up to 10 led to improved film crystallinity in the “in-plane” direction, which reduced surface roughness of the semicrystalline film. Treatment of the substrate surface by plasma results in different film coverage which was subsequently found to be governed by interaction of the deposited film and surface condition. Localized ferroelectric switching was substantially attained using piezo-force tip at 10 V on 10-monolayer films. Integrating this film as a dielectric layer into organic capacitor and field effect transistor yields a reasonably good leakage current (<10^?7 A/cm²) with hysteresis in capacitance and drain current with ON/OFF ratio of 10³ for organic ferroelectric memory application at significantly reduced operating voltage of |15| V.     

Improved interfacial quality of GaAs metal-oxide-semiconductor device with NH3-plasma treated yittrium-oxynitride as interfacial passivation layer

The interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with yittrium-oxynitride interfacial passivation layer treated by N₂ −/NH₃-plasma are investigated, showing that lower interface-state density (1.24 × 10¹² cm^− 2 eV^− 1 near midgap), smaller gate leakage current density (1.34 × 10^− 5 A/cm² at V_fb + 1 V), smaller capacitance equivalent thickness (1.43 nm), and larger equivalent dielectric constant (24.5) can be achieved for the sample with NH₃-plasma treatment than the samples with N₂ −/no-plasma treatment. The mechanisms lie in the fact that NH₃-plasma can provide not only N atoms, but H atoms and NH radicals to effectively passivate the high-k/GaAs interface, thus less pinning the Femi level at high-k/GaAs interface.     

Effects of electric field and bias voltage on corrosion behavior of tin under a thin electrolyte layer

The effects of electric field and bias voltage on corrosion behavior of tin under a thin electrolyte layer (TEL) were investigated by electrochemical and surface techniques. The results indicated that the order of the corrosion rate of tin under different electric fields with the same electric field gradient was as follows, square wave alternating current electric field (ACEF) > sinusoidal wave ACEF > direct current electric field (DCEF) > blank. Moreover, the corrosion rate of tin increased with increased direct current bias voltage under different electric fields. The contributions of electric field gradient and leakage current to the corrosion rate of tin were quantified under different electric fields with different bias voltages.