MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach

There is a need to explore circuit designs in new emerging technologies for their rapid commercialization to extend Moore’s law beyond 22 nm technology node. Carbon nanotube based transistor (CNFET) has significant potential to replace CMOS in the future due to its better electrostatics and higher mobility. This paper presents a complete optimal design of an inverting amplifier in CMOS, CNFET and hybrid technologies. We investigate and conceptually explain the performance measure of the amplifier at 32 nm technology node in terms of operating voltage, number of carbon nanotubes (CNT), diameter and pitch (inter-nanotube distance) variations of carbon nanotubes in a CNFET transistor in pure and hybrid technologies for area, power and performance optimization. This paper also explores the scope, possibilities and challenges associated with pure CNFET and hybrid amplifiers. We have found that pure CNFET amplifier provided good amplification while hybrid pCNFET-nMOS amplifier offered excellent frequency response and pMOS-nCNFET amplifier gave better transient performance compared with planar CMOS.     

Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling

The theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs) is examined by means of a general ballistic model. A novel approach is used to treat the SBs at the metal-nanotube contacts as mesoscopic scatterers by modifying the distribution functions for carriers in the channel. Noticeable current reduction is observed compared to previous ballistic models without SBs. Evanescent-mode analysis is used to derive a scale length and the potential profile near the contacts for radially symmetric CNFET structures. Band-to-band tunneling current and ambipolar conduction are also treated. The effects of different device geometries and different nanotube chiralities on the drain-current are studied using this simple model. Quantum conductance degradation due to SBs is also observed     

Nonlinear Characterization and Modeling of Carbon Nanotube Field-Effect Transistors

We report for the first time to our knowledge large-signal measurements performed at 600 MHz and in time domain on carbon nanotube field-effect transistors (CNFETs) using a large-signal network analyzer. To overcome the very high mismatch between the high CNFET impedance and the basic 50-$Omega$ configuration of the setup, the output impedance was matched with the help of an experimental active load–pull configuration. Hence, we were able to observe under large-signal conditions the nonlinear behavior of CNFETs. Static measurements and continuous-wave ${ S}_{ ij}$-parameter measurements were made for many different biases. They were used in order to determine a nonlinear electrical model that has been validated thanks to the nonlinear measurements. The developed model opens the way for electrical CNFET circuit simulation and nonlinear applications of these devices.      

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.     

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.     

Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies

As scaling of silicon devices continues at an aggressive pace, the problems associated with it are becoming more and more evident. With “short-channel effects” already in the way of scaling, interest has shifted to the possible use of nonsilicon molecular devices for circuit implementation. Carbon nanotube has emerged as a promising candidate. However, molecular devices such as carbon nanotube field-effect transistors (CNFETs) with their super-scaled dimensions and high current densities would increase the power density on chip and reasonable predictions estimate that they would far exceed the maximum power density limitation [1] . This paper explores the use of energy-recovery techniques in molecular CNFET based digital circuits and demonstrates how they can alleviate the power density problem in such circuits.     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability

Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential     

High-frequency response in carbon nanotube field-effect transistors

We report electrical measurements of the radio frequency response of carbon nanotube field-effect transistors (CNFETs). The very low current drive of CNFETs makes conventional high-frequency measurements difficult. To overcome this problem, we have used a novel approach to easily measure the response up to 250 MHz in nonoptimized experimental conditions. We observe a clear response of our CNFETs with no deterioration in signal up to at least 250 MHz, which is the limit for our present configuration.     

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.     

Efficient radix-r adders for nanoelectronics

In this study, a new design method and efficient designs for radix-r adders are proposed for carbon nanotube field effect transistor (CNFET) FET nanotechnology. This application also investigates the capability of the nanoscale device for designing high-performance analogue circuits. The proposed designs benefit from the unique electrical properties of CNFET, such as near-ideal current voltage characteristics, very high transconductance, high-performance switches and very high-performance and high-gain binary inverters, at nanoscale. Moreover, adjustable threshold voltage and the same mobility of electrons and holes in a CNFET facilitate the design and modification procedures. The proposed design can be considered as an instance of a general adder, capable of adding radix-r digits with high precision. It is noteworthy that a very limited number of carbon nanotube diameters for designing the proposed adder are needed, which enhance the manufacturability. The proposed circuits are designed based on arithmetic relations and are also verified at 32 nm feature size using HSPICE and the Stanford standard SPICE model.     

Examination of the high-frequency capability of carbon nanotube FETs

New results are added to a recent critique of the high-frequency performance of carbon nanotube field-effect transistors (CNFETs). On the practical side, reduction of the number of metallic tubes in CNFETs fashioned from multiple nanotubes has allowed the measured f_T to be increased to 30 GHz. On the theoretical side, the opinion that the band-structure-determined velocity limits the high-frequency performance has been reinforced by corrections to recent simulation results for doped-contact CNFETs, and by the ruling out of the possibility of favourable image-charge effects. Inclusion in the simulations of the features of finite gate-metal thickness and source/drain contact resistance has given an indication of likely practical values for f_T. A meaningful comparison between CNFETs with doped-contacts and metallic contacts has been made.     

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large-(digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET-device model incorporating the additional device/circuit-level non-idealities and multiple CNTs reported in the paper of Deng and Wong.     

Analytical modeling of high performance single-walled carbon nanotube field-effect-transistor

We present a novel analytical modeling of a zigzag single-walled semiconducting carbon nanotube field effect transistor (CNFET) by incorporating quasi-one-dimensional (Q1D) top-of-a-potential barrier approach. By implementing multimode carrier transport, we explore and compare the performance of a low- (360 cm²/Vs) and high-mobility (7200 cm²/Vs) CNFET model with experimental data from nanotube and 45 nm MOSFET, respectively, as well as existing compact models. Mobility and carrier concentration models are also developed to obtain a good matching with physical data. For a high mobility CNFET, we found that a maximum of 120 μA is obtained. In addition to this, a CNT-based inverter is also developed by constructing n-type and p-type CNFET in ORCAD’s analog behavioral model (ABM). A gain of as high as 5.2 is forecasted for an inverter of 80 nm CNFET.     

Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design

Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.     

Compact model for ballistic MOSFET-like carbon nanotube field-effect transistors

In this work, a compact model for MOSFET-like ballistic carbon nanotube field-effect transistors (CNFETs) is presented. The model is based on calculating the charge and surface potential on the top of the barrier between source and drain using closed-form analytical formulae. The formula for the surface potential is obtained by merging two simplified expressions obtained in two extreme cases (very low and very high gate bias). Two fitting parameters are introduced whose values are extracted by best fitting model results with numerically calculated ones. The model has a continuous derivative and thus it is SPICE-compatible. Accuracy of the model is compared to previous analytical model presented in the literature with numerical results taken as a reference. Proposed model proves to give less relative error over a wide range of gate biases, and for a drain bias up to 0.5 V. In addition, the model enables the calculation of quantum and gate capacitance analytically reproducing the negative capacitance behaviour known in CNFETs.     

Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron

This paper presents a performance comparison of a carbon nanotube-based field effect (CNFET)- and CMOS-based 6T SRAM cell at the 32 nm technology node. HSPICE simulations, carried out using Berkeley predictive technology model (BPTM), show that for a cell ratio and pull-up ratio of 1, CNFET-based 6T SRAM cell provides an improvement of 21% in read static noise margin (SNM) at VDD=0.4 V. The speed of CNFET cell is 1.84× that of CMOS cell. The standby leakage of CNFET cell is 84% less than CMOS cell. The process parameter variation results in 1.2% change in the read SNM of CNFET cell as compared with a wide variation of around 10.6% in CMOS cell.     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure

Scaling of silicon technology continues while a research has started in other novel materials for future technology generations beyond year 2015. Carbon nanotubes (CNTs) with their excellent carrier mobility are a promising candidate. The authors investigated different CNT-based field effect transistors (CNFETs) for an optimal switch. Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs were systematically compared from a circuit/system design perspective. The authors have performed a dc analysis and determined how noise margin and voltage swing vary as a function of tube diameter and power-supply voltage. The dc analysis of single-tube SB CNFET transistors revealed that the optimum CNT diameter for achieving the best I_ON-to-I_OFF ratio while maintaining a good noise margin is about 1 to 1.5 nm. Despite several serious technological barriers and challenges, CNTs show a potential for future high-performance devices as they are being researched     

Radio-frequency transmission properties of carbon nanotubes in a field-effect transistor configuration

In this letter, the radio-frequency (RF) transmission properties of single-walled carbon nanotubes (CNTs) have been characterized up to the frequency of 12 GHz in a carbon nanotube field-effect transistor (CNFET) configuration using a two-port S-parameter method for the first time. The RF characteristics of the CNTs were measured from the drain to the source of the CNFET. A resistance, inductance, and capacitance model has been proposed, and the element values have been extracted. Without the effect of the parasitics, the RF signal transmission in the CNTs presents no degeneration even at 12 GHz. The capacitive contact between CNTs and metal electrodes is reported.     

Design and analysis of a high-performance CNFET-based Full Adder

This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C _out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.