Sub-micron imaging on high-topography wafers using spray coating and projection lithography

We propose a method to image inside deep trenches (50 μm) using spray-coated resist and the ASML PAS 5500/100 system with the new functionality multi-step imaging. Multi-step imaging allows extending the focus offset range of the PAS 5500/100 system from ±30 μm to ±200 μm. Isolated trenches and contact holes were both imaged inside the deep trenches and on the surface of the wafer to study the versatility of the new functionality. A resolution of 700 nm in 3 μm thick photoresist, at the bottom of 50 μm deep, 200 μm wide trench, was obtained with this process. Finally, multi-focus exposure that consists in exposing the same image several times at various focus offsets was performed in order to image thick photoresist on high topographic substrates.     

B-Spline X-Ray Diffraction Imaging — Rapid non-destructive measurement of die warpage in ball grid array packages

Next generation “More than Moore” integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging (www.itrs.net [1]). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50 μm, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die.This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice misorientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50 μrad ≈ 0.003° in times as short as 9–180 s (worst case X–Y spatial resolution = 100 μm) for a full 8.7 mm × 8.7 mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package.     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

Direct imprint of Al foil for metallization of high-aspect ratio Al lines in nano/micro patterned SiO2/Si

Patterning techniques of Al micro/nano-structures become more and more critical as optical components and microelectronic devices continue to be scaled down. In this work, we fabricated gap-filled Al lines in SiO₂/Si masters by using the direct thermal imprint of molten Al. As a result, gap-filled Al lines with width ranging from 0.25 to 20 μm and depth ranging from 6 to 127 μm could be achieved without any further processing step such as CVD and PVD. The process studied here has shown the possibility to extend trench filling capability to 0.25 μm structures with 24:1 aspect ratio, which are difficult to be obtained by other conventional Al metallization methods.     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region

This paper reports the shallow trench isolation (STI)-induced mechanical stress-related Kink effect behaviour of the 40 nm PD SOI NMOS device. As verified by the experimentally measured data and the 2D simulation results, the Kink effect behaviour in the saturation region occurs at a higher V_D for the 40 nm PD device with a smaller S/D length (SA) of 0.17 μm as compared to the one with the SA of 1.7 μm due to the higher body-source bandgap narrowing (BGN) effect on the parasitic bipolar device (BJT) from the higher STI-induced mechanical stress, offset by the impact ionization (II) enhanced by the BGN in the high electric field region near the drain.     

Characteristics of a micromachined piezovalve combined with a multilayer ceramic actuator

This paper describes the design, fabrication and characteristics of a micromachined piezoelectric valve utilizing a multilayer ceramic actuator (MCA). The micromachined MCA valve, which uses a buckling effect, consists of three separate structures: the MCA, the valve actuator die and the seat die. The valve seat die with six trenches was made, and the actuator die, which is driven by the MCA under optimized conditions, was also fabricated. After Si wafer direct bonding between the seat die and the actuator die, the MCA was also anodically bonded to the seat/actuator die structure. A polydimethylsiloxane (PDMS) sealing pad was fabricated to minimize the leak rate. Finally, the PDMS sealing pad was also bonded to the seat die and the stainless steel package. The MCA valve shows a flow rate of 9.13 sccm at an applied DC voltage of 100 V with a 50% duty cycle and a maximum non-linearity of 2.24% FS. Therefore, the fabricated MCA valve is suitable for a variety of flow control equipment, as a medical bio-system and in the automobile industry.     

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias

The reliability results for barrier/liner systems in different high aspect ratio (5 × 50 μm) through silicon vias (TSV) are presented. Quite a few factors can influence the TSV barrier/liner reliability performance, including the TSV trench etch process, the oxide liner material/thickness, etc. The challenges for more advanced TSV technology nodes (e.g. 3 × 40 μm) are also discussed and possible solutions are proposed.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

Effect of additive N2 and Ar gases on surface smoothening and fracture strength of Si wafers during high-speed chemical dry thinning

In this work, we investigated the changes in the surface roughness and fracture strength of bare or mechanically ground Si wafers caused by high-speed chemical dry etching. High-speed chemical dry thinning was achieved by injecting NO gas and additive N₂ and Ar gases directly into the reactor during the supply of F radicals from NF₃ remote plasmas. With the additional injection of N₂ and Ar gases, together with the direct-injected NO gas, the rough surfaces of the mechanically ground Si wafers could be effectively smoothened while keeping the thinning rate of Si very fast, viz. up to 18.2 μm/min. The additive N₂ gas reduced the wafer surface temperature after thinning. The fracture strength of the Si wafers thinned down to 50 μm by the chemical dry etching process was more highly increased, due to the more effective removal of the mechanical damage and stress generated during the mechanical grinding process, as compared to the other final thinning methods such as lapping or plasma etching. The results indicated that the high-speed dry chemical thinning process could be used for the ultra-thin final thinning of Si wafers for next generation three-dimensional packaging technologies.     

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm² and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm² have been achieved without any modification of existing standard CMOS process.     

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

Electroplating is the best process for the manufacture of fine pitch flip chip solder bumps. However, certain unstable electroplating parameters usually cause poorer coplanarity, which affects packaging reliability and yield. This paper attempts to utilize a CMP-like polisher to reduce the nonuniform height deviation after electroplating. The optimization of three major polishing parameters—pad hardness, loading pressure, and polishing speed—enables the polisher to have a higher material removal rate (MRR) and an easier manipulation as compared with chemical mechanical polishing (CMP). After polishing at a pitch size of 100 μm, the overall coplanarity could be decreased sharply from 33±2.5 μm (coplanarity=7.5%) to 28±1 μm (coplanarity=3%) and it even reached 26±0.5 μm (coplanarity=1%) after reflow.     

RF measurements to pinpoint defects in inkjet-printed,thermally and mechanically stressed coplanar waveguides

In this work 10-GHz-band RF measurement and microscopy characterizations were performed on thermally and mechanically long-term-stressed coplanar waveguides (CPW) to observe electrical and mechanical degradation in 1-mm-thick PPO/PPE polymer substrates with inkjet-printed Ag conductors. The structure contained two different CPW geometries in a total of 18 samples with 250/270 μm line widths/gaps and 670/180 μm line widths/gaps. A reliability test was carried out with three sets. In set #1 three 250 μm and three 670 μm lines were stored in room temperature conditions and used as a reference. In set #2 six samples were thermally cycled (TC) for 10,000 cycles, and in set #3 six samples were thermally cycled and bent with 6 mm and 8 mm bending diameters.Thermal stressing was done by cycling the samples in a thermal cycling test chamber operating at 0/100 °C with 15-minutes rise, fall, and dwell times, resulting in a one-hour cycle. The samples were analyzed during cycling breaks using a vector network analyzer (VNA). In addition to optical microscopy, field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM) imaging were used to mechanically characterize the structures.The results showed that the line width of 670 μm had better signal performance and better long-term reliability than the line width of 250 μm. In this study, the average limit for proper RF operation was 2500 thermal cycles with both line geometries. The wide CPW lines provided more stable characteristics than the narrow CPW lines for the whole 10,000-cycle duration of the test, combined with repeated bending with a maximum bending radius of 6 mm. A phenomenon of nanoparticle silver protruding from cracks in the print of the bent samples was observed, as well as fracturing of the silver print in the CPW lines.     

MEMS based low cost piezoresistive microcantilever force sensor and sensor module

In the present work, we report fabrication and characterization of a low-cost MEMS based piezoresistive micro-force sensor with SU-8 tip using laboratory made silicon-on-insulator (SOI) substrate. To prepare SOI wafer, silicon film (0.8 µm thick) was deposited on an oxidized silicon wafer using RF magnetron sputtering technique. The films were deposited in argon (Ar) ambient without external substrate heating. The material characteristics of the sputtered deposited silicon film and silicon film annealed at different temperatures (400–1050 °C) were studied using atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques. The residual stress of the films was measured as a function of annealing temperature. The stress of the as-deposited films was observed to be compressive and annealing the film above 1050 °C resulted in a tensile stress. The stress of the film decreased gradually with increase in annealing temperature. The fabricated cantilevers were 130 μm in length, 40 μm wide and 1.0 μm thick. A series of force–displacement curves were obtained using fabricated microcantilever with commercial AFM setup and the data were analyzed to get the spring constant and the sensitivity of the fabricated microcantilever. The measured spring constant and sensitivity of the sensor was 0.1488 N/m and 2.7 mV/N. The microcantilever force sensor was integrated with an electronic module that detects the change in resistance of the sensor with respect to the applied force and displays it on the computer screen.     

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.     

Projection lithography to print thick resist patterns with triangular and semi-circular cross-section profiles

Patterning technology to print thick resist patterns with triangular and semi-circular cross-section profiles was investigated for applying to fabrication of light-guide plates and lens arrays, surface texturization of solar cells, and others. Positive novolac resist PMER P-LA900PM with an initial thickness of 10 μm was used and the patterns were mainly printed by the exposure light with a wavelength of 405 nm. At this wavelength, the light transmittance through the resist film was 0.5% and 80% before and after the exposure, respectively. Caused by this moderate transmittance characteristics, pattern sidewalls suitably inclined or roundly curved. When 400 μm line-and-space reticle patterns were printed using a projection exposure lens with a reduction ratio of 1/19 and a numerical aperture of 0.125, triangular patterns were obtained under the defocus conditions of around ?100 μm. The sidewall angle was widely controlled between 20° and 55° by mainly changing the exposure time. On the other hand, semi-circular profiles were obtained when patterns were printed at the defocus position of +100–200 μm. It was clarified that the circular radius depended only on the defocus position and did not depend on the exposure time. Patterns with circular radiuses of 9–34 μm were successfully obtained.     

Accurate operation of a CMOS integrated temperature sensor

A high-accuracy temperature sensor is designed by applying the temperature characteristics of substrate bipolar transistor in CMOS technology. Initial accuracy of the temperature sensor can be improved by chopper amplifiers and dynamic element matching. Using these two methods, the circuit realization of reference voltage is also described. Simulation results show that the inaccuracy is within×0.4 °C from ?40 to +100 °C. Experimental results, obtained from circuits fabricated in 0.5 μm CMOS process, indicate that the sensor is inaccurate within×0.7 °C from ?40 to +100 °C. The power dissipation is 0.35 mW and the chip area is 889 μm×620 μm. Compared with previously reported work, the temperature sensor in the paper has lower inaccuracy without calibration.     

Integration of organic semiconductor lasers and single-mode passive waveguides into a PMMA substrate

Efficiently combining active and passive elements in integrated optics is a key ingredient for their successful employment. Here, we present the fabrication of an optimized PMMA substrate structure for improved coupling of laser light generated by organic semiconductor distributed feedback lasers into single-mode deep ultraviolet induced waveguides. For production, electron beam lithography on an oxidized silicon wafer and subsequent reactive ion etching is used to form the feedback grating of the laser. Afterwards, an aligned second electron beam lithography step on top of the grating allows the fabrication of a topographical step of 1.67 μm on the edges of the grating area. Metal is evaporated on this resulting master structure serving as a plating base for electroforming of a Ni tool. The tool is then used for hot embossing of the structure into PMMA bulk material. On a length of 500 μm the imprinted grating lines, having a period of 200 nm, are 100 nm wide and 60 nm high. Aligned deep ultraviolet exposure to induce a passive single- or multi-mode waveguide and co-evaporation of the active material Alq₃:DCM finish the coupling region. This structure optimizes the coupling of laser light generated in the laser structure into the passive waveguide. In combination with microfluidic channels, the laser light can be considered for sensing applications on a PMMA lab-on-chip system.     

Invited paper: Short pulse generation in mid-IR fiber lasers

Mode-locked fiber lasers emitting short pulses of light at wavelengths of 2 μm and longer are reviewed. Rare-earth doped silica and fluoride fiber lasers operating in the mode-locked regime in the mid-IR (2–5 μm) have attracted attention due to their usefulness to spectroscopy, nonlinear optics, laser surgery, remote sensing and ranging to name a few. While silica fiber lasers are fundamentally limited to emission wavelengths below 2.2 μm, fluoride fiber lasers can reach to nearly 4 μm. The relative infancy of fluoride fibers as compared to silica fibers means the field has work to do to translate the mode-locking techniques to systems beyond 2 μm. However, with the recent demonstration of a stable, mode-locked 3 μm fiber laser, the possibility of achieving high performance 3 μm class mode-locked fiber lasers looks promising.