Single-electron effect in PtSi/porous Si Schottky junctions

PtSi/porous Si schottky junctions exhibit a breakdown type current-voltage (I-V) curve in reverse bias mode. Below breakdown their current density is much less than regular PtSi/Si junctions. The breakdown voltage decreases with application of infrared radiation for both n and p-type junctions. N-type junctions are sensitive to IR wavelengths of up to 7 /spl mu/m even at room temperature. The small reverse bias current, the change of breakdown voltage with radiation, and IR sensitivity at room temperature can all be explained by single-electron effect. Numerical results show that representative porous schottky junctions exhibit depletion capacitances in 10/sup -19/ f range which is enough to observe single-electron effect at room temperature. Single-electron effect and avalanche multiplication can explain existing experimental data.     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

MoS2势垒层磁性隧道结的温度-偏压特性研究

MoS₂是一种具有特殊能带结构的二维半导体材料,当层数较少时,其带隙会随层数显著减小。因此,基于MoS₂势垒层的磁性隧道结会展现出更丰富的物理特性。文章通过理论计算分别得到了单层、双层、三层以及五层MoS₂势垒层磁性隧道结的温度-偏压相图,研究了铁磁电极半交换劈裂能对相图特性的影响。计算结果表明：单层和三层MoS₂势垒层磁性隧道结适合应用于低温器件中。其中,单层MoS₂势垒层磁性隧道结在高功率工作环境下具有优异的性能。双层MoS₂势垒层磁性隧道结的优化区域位于室温和低偏压区,因此适用于信息存储领域。五层MoS₂势垒层磁性隧道结可通过调节铁磁电极参数使其工作在较宽的功率范围内。上述研究结果为MoS₂势垒层磁性隧道结的应用奠定了坚实的理论基础。     

Some properties of ion-implanted p−n junctions in silicon

Diodes have been made by implantation of boron or gallium ions in n-type, and phosphorus ions in p-type silicon. The doses range from 5 × 10¹² to 10¹⁵ ions/cm², and the energies from 20 to 70 keV. In all diodes the reverse current shows a sharp recovery step upon annealing at 500–600°C. The reverse current after this annealing is typically of the order of 1 nA/cm² at 1 V reverse bias. To overcome the problem of low breakdown voltages usually found for implanted junctions, methods have been developed to enlarge the effective radius of curvature at the edge of the implanted junction. In a planar process with oxide masking, breakdown voltages of 150 V for 3 Ωcm or 1500 V for 300 Ωcm silicon are obtained. This is done by implanting the ions through a tapered oxide, where the oxide walls make an angle of only 3–5° with the silicon surface. The junction depth in this case is 0.4 μm.Another method uses a mask, placed free in front of the slice. Slice and mask rotate during implantation. In this way, a breakdown voltage of 2700 V is obtained with 300 Ωcm silicon.     

High-voltage (1800 V) planar 4<Emphasis Type="Italic">H</Emphasis>-SiC <Emphasis Type="Italic">p-n</Emphasis> junctions with floating guard rings

Planar 4H-SiC p-n junctions with floating guard rings have been fabricated. The main junction and the rings were formed by room temperature boron implantation followed by high temperature annealing. The breakdown voltage of the p-n junctions is 1800 V, which twice exceeds that of similar junctions without guard rings and reaches 72% of the calculated breakdown voltage of a plane-parallel p-n junction with the same epitaxial layer parameters     

Magnetic Tunnel Junctions for Spintronic Memories and Beyond

In this paper, recent developments in magnetic tunnel junctions (MTJs) are reported with their potential impacts on integrated circuits. MTJs consist of two metal ferromagnets separated by a thin insulator and exhibit two resistances, low (R_p) or high (R_ap) depending on the relative direction of ferromagnet magnetizations, parallel (P) or antiparallel (AP), respectively. Tunnel magnetoresistance (TMR) ratios, defined as (R_ap $R_p)/R_p as high as 361%, have been obtained in MTJs with Co₄₀Fe₄₀B₂₀ fixed and free layers made by sputtering with an industry-standard exchange-bias structure and post deposition annealing at Ta = 400 degC. The corresponding output voltage swing DeltaV is over 500 mV, which is five times greater than that of the conventional amorphous Al-O-barrier MTJs. The highest TMR ratio obtained so far is 500% in a pseudospin-valve MTJ annealed at Ta = 475 degC, showing a high potential of the current material system. In addition to this high-output voltage swing, current-induced magnetization switching (CIMS) takes place at the critical current densities (J_CO) on the order of 10⁶ A/cm² in these MgO-barrier MTJs. Furthermore, high antiferromagnetic coupling between the two CoFeB layers in a synthetic ferrimagnetic free layer has been shown to result in a high thermal-stability factor with a reduced J_CO compared to single free-layer MTJs. The high TMR ratio enabled by the MgO-barrier MTJs, together with the demonstration of CIMS at a low J_CO, allows development of not only scalable magnetoresistive random-access memory with feature sizes below 90 nm but also new memory-in-logic CMOS circuits that can overcome a number of bottlenecks in the current integrated-circuit architecture     

Integrity of shallow junction CMOS structures with Ti/TiN/Al---Si---Cu and Ti/TiN/Al---Cu contact metallization

Shallow junction complementary metal oxide semiconductor (CMOS) structures (0.25 and 0.35 μm depth) were studied using sputter deposited Ti/TiN/Al---Si---Cu and Ti/TiN/Al---Cu films for contact metallization. Single contact Van de Pauw patterns (to measure the breakdown voltage) as well as large junction area structures with multiple contact windows were used for electrical measurements. An increase in the RTA temperature used to silicide the contacts increased the Si consumption in the junctions and resulted in degradation of junctions yields. The thickness of the Ti layer had a larger influence on the stability of the junction than the thickness of the TiN layer (in the range of thicknesses studied). Al---Si(0.75 wt%)---Cu(0.5 wt%) films are more stable than Al---Cu(0.5 wt%) films for junction spiking. The Al---Cu films are more reactive, and the interdiffusion of Ti into the Al---Cu films makes the junctions less stable. The annealing temperature and post wafer fabrication is critical in maintaining stability of junctions. The junction depths, and dopants (BF₂-p- and As n-implanted) used in forming the junctions affect the breakdown voltages and junction yields. The BF₂ implanted junctions are more stable than arsenic implanted junctions.     

Total ionizing dose effects and annealing behavior for domestic VDMOS devices

Total dose effects and annealing behavior of domestic n-channel VDMOS devices under different bias conditions were investigated. The dependences of typical electrical parameters such as threshold voltage, breakdown voltage, leakage current, and on-state resistance upon total dose were discussed. We also observed the relationships between these parameters and annealing time. The experiment results show that: the threshold voltage negatively shifts with the increasing of total dose and continues to decrease at the beginning of 100 ℃ annealing; the breakdown voltage under the drain bias voltage has passed through the pre-irradiation threshold voltage during annealing behaving with a "rebound" effect; there is a latent interface-trap buildup (LITB) phenomenon in the VDMOS devices; the leakage current is suppressed; and on-state resistance is almost kept constant during irradiation and annealing. Our experiment results are meaningful and important for further improvements in the design and processing.     

Properties of Be-implanted planar GaAs p-n junctions

The fabrication and characteristics of planar junctions in GaAs formed by Be ion implantation are discussed. The critical processing step is shown to be the use of a carefully deposited oxygen-free Si/SUB 3/N/SUB 4/ encapsulation during post-implantation annealing. Forward and reverse characteristics are presented for Be-implanted junctions formed by encapsulating with SiO/SUB 2/, Si/SUB x/O/SUB y/N/SUB z/, or Si/SUB 3/N/SUB 4/ layers prior to annealing at 900/spl deg/C. Junctions which exhibit leakage current density of ~2/spl times/10/SUP -7/ A/cm/SUP 2/ at 80 V reverse bias and breakdown voltage >200 V have been fabricated using RF-plasma deposited Si/SUB 3/N/SUB 4/ layers as the encapsulant.     

退火温度对Fe_(40)Co_(40)Zr_7Nb_2AlB_9Cu合金的结构、热行为及磁性能的影响

采用单辊快淬法制备了Fe40Co40Zr7Nb2AlB9Cu非晶合金薄带,在不同温度下对其进行等温退火处理。研究了退火温度对合金的结构、热行为和磁性能的影响。结果表明:Fe40Co40Zr7Nb2AlB9Cu非晶合金的DTA曲线存在2个晶化放热峰,晶化激活能分别为267.3 kJ/mol和188.3 kJ/mol。其晶化过程为:非晶→非晶+α-FeCo→α-FeCo+Co2Zr+ZrCo3B2+Fe(Co)3Zr。α-FeCo相的晶化体积分数和晶粒尺寸随退火温度的升高而逐渐增大。低于873 K退火时,矫顽力变化不明显;873 K退火时,矫顽力达到最小值0.27 kA/m;高于873 K退火时,矫顽力逐渐增大。     

DC characterization of fully ion-implanted p-n junctions intosemi-insulating InP

The forward and reverse characteristics of p⁺-n junctions made by Mg and Si implantation and rapid thermal annealing into Fe-doped semi-insulating InP are described. The effects of the Si dose for obtaining the n-type region, the use of P co-implantation for obtaining the p⁺ region, and the annealing time are studied. The dominant conduction mechanism at forward bias was found to be recombination in the space-charge region, with ideality factors of n=2 down to 198 K, and temperature dependence with an activation energy of 0.76 eV. The reverse characteristics presented junction breakdown at voltages around -20 V, and were accurately described by a thermally-activated trap-assisted tunneling mechanism. The energy of the corresponding trap, obtained by the fitting of the experimental characteristics, was 0.6 eV, and its origin was tentatively ascribed to the Fe deep acceptor present in semi-insulating InP     

Transport and storage properties of CrSi2/Si junctions made using the CAPVD technique

p-CrSi₂/n-crystSi and p-CrSi₂/p-crystSi hetero junctions produced by cathodic arc physical vapor deposition were worked out by means of capacitance–voltage–temperature (C–V–T) and current–voltage–temperature (I–V–T) measurements to investigate storage and transport properties. Former measurement on p-CrSi₂/n-crystSi structure confirmed an abrupt type junction together with a building voltage at the proximity of 0.7 V. Though a fairly well rectification ratio (10³ at ±2 V) was realized by I–V measurement, it became deteriorated with the increase in ambient temperature. From temperature dependence of I–V variations, distinct conduction mechanisms were identified. In forward (reverse) direction trap assisted single-multistep tunneling recombination (generation) and space-charge limited current flow that corresponded to low and high bias voltage regions, respectively, were identified. Moreover, an activation energy (E_A) determined from the slopes of I–V–T curves as 0.22 and 0.26 eV was interpreted as the energy position of a chromium–boron (Cr–B) complex-type point defect residing in n/p doped c-Si semiconductor in CrSi₂/n–c-Si and CrSi₂/p–c-Si junctions. The retrieved E_A was in agreement with the recent DLTS measurement. Based on the experimental observations, schematic current path was built to interpret I–V/C–V behaviors. The model was successful in explaining the decrease in measured capacitance under large forward bias voltage reported for the first time by us for the present CrSi₂/Si junctions.     

1330 V, 67 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC(0001) RESURF MOSFET

Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented.     

High performance n/p and p/n germanium diodes at low-temperature activation annealing

In this work we demonstrate the fabrication and characterization of high performance junction diodes using annealing temperatures within the temperature range of 300-350 °C. The low temperature dopant activation was assisted by a 50 nm platinum layer which transforms into platinum germanide during annealing. The fabricated diodes exhibited high forward currents, in excess of 400 A/cm² at ∼|0.7| V for both p⁺/n and n⁺/p diodes, with forward to reverse ratio I_F/I_R greater than 10⁴. Best results for the n⁺/p junctions were obtained at the lower annealing temperature of 300 °C. These characteristics compare favorably with the results of either conventional or with Ni or Co assisted dopant activation annealing. The low-temperature annealing in combination with the high forward currents at low bias makes this method suitable for high performance/low operating power applications, utilizing thus high mobility germanium substrates.     

退火温度对ZrO_2高介电薄膜电学性能的影响

利用反应磁控溅射法沉积了ZrO2介电薄膜,研究了退火温度对ZrO2介电薄膜电学性能的影响,并对漏电流最小的样品的漏电流机制进行了分析。结果表明,随着退火温度的升高,漏电流先减小后增大,退火温度为300℃时所制备薄膜的漏电流最小,当所加电压为–1.4 V时,漏电流密度为8.32×10–4 A/cm2。当所加正偏压为0-0.8 V和0.8-4.0 V时,该样品的漏电流主导机制分别为肖特基发射和直接隧穿电流;当所加负偏压为–1.7-0 V和–4.0-–1.7 V时,其主导机制分别为肖特基发射和空间电荷限制电流。     

Implications of low breakdown voltage of component subcells on external quantum efficiency measurements of multijunction solar cells

The electrical and optical coupling between subcells in a multijunction solar cell affects its external quantum efficiency (EQE) measurement. In this study, we show how a low breakdown voltage of a component subcell impacts the EQE determination of a multijunction solar cell and demands the use of a finely adjusted external voltage bias. The optimum voltage bias for the EQE measurement of a Ge subcell in two different GaInP/GaInAs/Ge triple‐junction solar cells is determined both by sweeping the external voltage bias and by tracing the I–V curve under the same light bias conditions applied during the EQE measurement. It is shown that the I–V curve gives rapid and valuable information about the adequate light and voltage bias needed, and also helps to detect problems associated with non‐ideal I–V curves that might affect the EQE measurement. The results also show that, if a non‐optimum voltage bias is applied, a measurement artifact can result. Only when the problems associated with a non‐ideal I–V curve and/or a low breakdown voltage have been discarded, the measurement artifacts, if any, can be attributed to other effects such as luminescent coupling between subcells. Copyright © 2015 John Wiley & Sons, Ltd.     

The effects of thermal annealing on the electrical characteristics of Au/n–InP/In diode

An Au/n–InP/In diode has been fabricated in the laboratory conditions and the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the diode have been measured in room temperature. In order to observe the effect of the thermal annealing, this diode has been annealed at temperatures 100 and 200 °C for 3 min in N₂ atmosphere. The characteristic parameters such as leakage current, barrier height and ideality factor of this diode have been calculated from the forward bias I–V and reverse bias C–V characteristics as a function of annealing temperature. Also the rectifying ratio of the diode is evaluated for as-deposited and annealed diode.     

Fe_(81)Zr_7Nb_2B_(10)和Fe_(78)Co_(2.5)Zr_7Nb_2B_(10)Cu_(0.5)合金的热性能、微观结构及磁性能研究

采用单辊快淬法制备了Fe81Zr7Nb2B10和Fe78Co2.5Zr7Nb2B10Cu0.5非晶合金,在不同温度下对两种合金进行了热处理。利用差热分析仪(DTA)、X射线衍射仪(XRD)和振动样品磁强计(VSM)等仪器对两种合金的热性能、微观结构和磁性能进行了测试分析。结果表明在Fe78Co2.5Zr7Nb2B10Cu0.5合金的晶化过程中存在预结晶效应,而在Fe81Zr7Nb2B10合金的晶化过程中没有。Fe81Zr7Nb2B10和Fe78Co2.5Zr7Nb2B10Cu0.5合金经803 K退火后,分别有α-Fe和α-Fe(Co)相从非晶基体中析出。随退火温度的升高,两种合金的比饱和磁化强度(Ms)变化趋势相似,但矫顽力(Hc)变化趋势明显不同。     

退火温度对Au/Ti/4H-SiC肖特基接触特性的影响

采用电子束蒸发法在4H-SiC表面制备了Ti/Au肖特基电极,研究了退火温度对Au/Ti/4H-SiC肖特基接触电学特性的影响.对比分析了不同退火温度下样品的电流密度-电压(J-V)和电容-电压(C-V)特性曲线,实验结果表明退火温度为500℃时Au/Ti/4H-SiC肖特基势垒高度最大,在.J-V测试和C-V测试中分别达到0.933 eV和1.447 eV,且获得理想因子最小值为1.053,反向泄漏电流密度也实现了最小值1.97×10-8 A/cm2,击穿电压达到最大值660 V.对退火温度为500℃的Au/Ti/4H-SiC样品进行J-V变温测试.测试结果表明,随着测试温度的升高,肖特基势垒高度不断升高而理想因子不断减小,说明肖特基接触界面仍然存在缺陷或者横向不均匀性,高温下的测试进一步证明肖特基接触界面还有很大的改善空间.     

Crystalline CoFeB/Graphite Interfaces for Carbon Spintronics Fabricated by Solid Phase Epitaxy

Structurally ordered interfaces between ferromagnetic electrodes and graphene or graphite are of great interest for carbon spintronics, since they allow spin‐filtering due to k‐vector conservation. By solid phase epitaxy of amorphous/nanocrystalline CoFeB at elevated temperatures, the feasibility of fabricating crystalline interfaces between a 3d ferromagnetic alloy and graphite is demonstrated, without suffering from the unwetting problem that was commonly seen in many previous studies with 3d transition metals. The films fabricated on graphite in this way are found to have a strong body‐centered‐cubic (110) texture, albeit without a unique, well‐defined in‐plane epitaxial relationship with the substrate lattice. Using various X‐ray spectroscopic techniques, it is shown that boron suppresses the formation of CoFe‐O during CoFeB deposition, and then diffuses out of the CoFe lattice. Segregation of B occurred exclusively to the film surface upon in situ annealing, and not to the interface between CoFeB and graphite. This is favorable for obtaining a high spin polarization at the hybrid CoFe/graphite crystalline interface. The Co and Fe spin moments in the crystalline film, determined by X‐ray magnetic circular dichroism, are found to be bulk‐like, while their orbital moments show an unusual giant enhancement which has yet to be understood.