Heuristic receiver for implantable UWB applications

High data rate implantable wireless systems come with many challenges, chief among them being low power operation and high linearity. A low noise amplifier (LNA) designed for this application must include high gain, low noise figure (NF) and better linearity at low power consumption within the required frequency band. The down converter also requires a passive mixer to achieve low power and better linearity. In this paper, design is based on an Impulse Response (IR) Ultra-wideband (UWB) receiver operating at (3.1–5) GHz implemented in 0.25 μm CMOS Silicon on Sapphire (SOS). This paper reports the design and measurement of a UWB receiver with a designed and measured linearity of 17 dBm, a gain of 30.5 dB and a minimum NF of 4.5 dB, which make it suitable for implantable radio applications.     

A high-gain low-power 2–14 GHz ultra-wide-band CMOS LNA for wireless receivers

In this paper, a 2–14 GHz CMOS LNA for ultra-wide-band (UWB) wireless systems is presented. To achieve a good and flat high power gain along with a low noise figure and a high input return loss, the proposed LNA adopts a capacitive cross-coupling common-gate (CG) topology with extra cascaded transistors and inductance. Over the entire 2–14 GHz bandwidth, it exhibits a return loss less than ?10 dB and a small-signal gain of 9 dB. With an input intercept point of ?3 dBm at 5 GHz, it consumes only 9 mW from a 1.5 V supply voltage.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Low power high data rate wireless endoscopy transceiver

A low power high data rate wireless endoscopy transceiver is presented. Transceiver architecture, circuit topologies and design trade-offs have been considered carefully to satisfy the tight requirements of the medical endoscopy capsule: lower power consumption, high integration degree and high data rate. The prototype, implemented in 0.25 μm CMOS, integrates a super-heterodyne receiver and a super-heterodyne transmitter on a single chip together with an integrated RF local oscillator and LO buffers. The digital modulation and demodulation is also implemented in analog field and no data converters are needed for the whole endoscopy capsule. The measured sensitivity of the receiver is about −70 dBm with a data rate 256 kbps, and the measured output power of the transmitter could achieve −23 dBm with a data rate 1 Mbps. The transceiver operates from a power supply of 2.5 V, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode.     

A printed monopole ellipzoidal UWB antenna with four band rejection characteristics

An antenna design with four band rejection characteristics for UWB application is demonstrated. The proposed unique UWB antenna has shape of an embedded ellipse at top of trapezoidal patch (named as ellipzoidal), 50 Ω impedance microstrip line feed and a truncated beveled ground plane. To realize four band stop characteristics, three inverted U-shaped and a single I-shaped slots each of half guided wavelength are utilized on radiating element. The fabricated antenna has dimensions of 27 mm × 36 mm × 1.6 mm. This four band notched ellipzoidal UWB antenna has measured frequency bandwidth 2.8–14 GHz for magnitude of S₁₁ < −10 dB level. The measured ellipzoidal antenna exhibits four band rejection characteristics for magnitude of S₁₁ > −10 dB at 3.55 GHz for WiMAX band (3.26–3.9 GHz), 4.55 GHz for ARN band (4.35–5.05 GHz), 5.7 GHz for WLAN band (5.5–6.65 GHz) and 8.8 GHz for ITU-8 band (7.95–9.35 GHz). The proposed ellipzoidal UWB antenna maintains omnidirectional radiation pattern, gain, linear phase response, <1 ns group delay, and transfer function in the whole UWB operating bandwidth except at notched frequency bands.     

Oscillation-controlled CMOS ring oscillator for wireless sensor systems

This paper presents a ring oscillator with the function of the oscillation controlled for wireless sensor systems (WSSs). The proposed oscillator consists of a NAND gate, 4 inverters, and 1-, 3-, 9-times buffer stage. Operation of it is controlled by the NAND gate. The oscillator can reduce the power loss because the oscillator is oscillated during only high level input. The proposed oscillator was designed and fabricated by 2.5 μm CMOS technology, through which it is possible to realize a WSS on a single chip because a sensor and an oscillator can be fabricated concurrently.The frequency tuning range of the oscillator was found to be approximately 90–152 MHz and the output power of the oscillator was ?8.42 dBm. The measured phase noise is ?99.35 and ?102.59 dBc/Hz at 1 and 5 MHz offsets, respectively, from the carrier of 152 MHz. Power consumption of the oscillator is determined by the duty cycle of the input signal pulse, and the range of power consumption was measured as 1.5–45 mW at the duty cycle of 1.0.     

A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35 μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1 dB, gain of 18.9–20.2 dB, gain flatness of ±0.65 dB, input third order intercept point (IIP₃) of ?7 dBm at 6 GHz, exhibits less than 16 ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18 mW.     

A novel configuration for UWB LNA suitable for low-power and low-voltage applications

Two UWB LNAs based on a new configuration suitable for low-power and low-voltage applications are presented. The proposed configuration saves bias circuit because of sharing only a bias circuit. In designing LNA-1 good phase linearity property achievement is followed for low-power and low-voltage applications, while in LNA-2 the main concerns are high power gain, by keeping low-power consumption, and small chip area. By taking advantages of resistive-feedback and RLC load, wideband input matching is obtained. Based on the proposed configuration, accompany with complete noise analysis, noise of LNA-2 is highly suppressed and flat noise figure is reaped. The 130 nm CMOS LNA-1 and LNA-2 dissipate 2.95 mW and 6.09 mW, respectively, from 0.7 V supply voltage, without using of forward-body-bias technology. Input return loss of both LNAs is below than ?10.5 dB while LNA-1 achieves average power gain of 9 dB and LNA-2 17 dB. The group-delay variation of LNA-1 is about ±6.1 ps over the band of 3.1–10.6 GHz. The NF of LNA-2 is 2.4–2.89 dB over the whole band of interest.     

A tunable CMOS Wilkinson power divider using active inductors

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.     

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15 MHz LP bandwidth, 2–8 MHz CBP bandwidth and 0–36 dB gain range with 1 dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65 nm CMOS. It achieves 15.2 dB m/27.1 dB m IB/OB-IIP3, −2 dB m IP1dB and 71 dB m IIP2 while consuming 3.6–9.1 mW from a 1.2 V power supply and 0.75 mm² chip area.     

Dual band monopole antenna based on metamaterial structure with narrowband and UWB resonances with reconfigurable quality

In this article, an Ultra Wide Band (UWB) monopole antenna based on Metamaterial (MTM) unit cell with reconfigurable feature has been developed. The proposed antenna covers 3.1–10.6 GHz for UWB applications and it has a reconfigurable narrow-band for L-band (1.27 GHz) and wireless applications. The gaps in Split Rings Resonator (SRR) element are made for the Left-hand capacitance and Ω-shape strip layer by four via junctions are used for Left-hand inductance. The antenna is printed on FR-4 low cost substrate with relative permittivity of 4.4 and thickness of 1.6 mm. The total size of the antenna is 40 mm × 40 mm. The simulation is carried out using HFSS commercial full-wave software. In addition, the experimental results are presented and compared with simulated results. The antenna gives a maximum peak gain of 6 dBi with Omni-Directional radiation pattern and high efficiency of more than 70%. By embedding four switches in Ω-shape strip layer, a reconfigurable antenna has been successfully designed for wireless applications with sufficient qualification. The monopole part covers the UWB spectrum and the CRLH is responsible for the controllable narrowband resonance. The simulation and experimental results are confirmed by the numerical results.     

Compact circular-patch-based bandpass filter for ultra-wideband wireless communication systems

Ultra-wideband (UWB) is a radio technology that enables low-power-level, short-range, and wide-bandwidth communication, and it has been widely applied in personal area networks, precision geolocation, medical, surveillance, and vehicular radar systems. Since Federal Communications Commission released the unlicensed use of the UWB range (3.1–10.6 GHz), a significant attention has been paid to the development of UWB devices, particularly UWB bandpass filters. In this paper, we propose a novel UWB bandpass filter based on circular patch resonator that is grounded by via and perturbed by slits and defected ground structures. The resonator’s behaviour is analysed in detail and it is shown that its specific configuration allows a flexible control of the three lowest resonant modes, which are used to form UWB passband. To demonstrate the potential of the resonator, a UWB filter has been designed, fabricated, and measured. The filter is characterized by the insertion loss lower than 1 dB and return loss higher than 17 dB within the passband, as well as by very small group delay variation of only 0.07 ns. Also, the filter exhibits suppression higher than 19 dB up to 30 GHz, and very small overall dimensions of only 0.31λ_g × 0.31λ_g, and thus it outperforms other published UWB filters.     

Design of a novel bandwidth-enhanced double-slot TSA and analysis according to the microwave network theory

In this paper, a novel bandwidth-enhanced ultra-wideband (UWB) tapered slot antenna with Y-shaped corrugated edges, is proposed. In the double-slot structure, the two slots are separated by a V-shaped metal surface with straight edges, which is beneficial to improve the directivity of the antenna. Meanwhile, an exponential Y-shaped corrugated edge is designed. This novel corrugated edge can not only improve the impedance bandwidth, but also enhance the gain of the antenna. Additionally, according to the theory of microwave network, this paper analyzes the reason of bandwidth enhancement realized by double-slot structure. The proposed antenna provides 167% fractional bandwidth from 2.5 GHz to 28 GHz. The gain of the proposed antenna is more than 10 dB from 3.5 GHz to 25 GHz, and more than 8 dB at the whole operating band.     

A modified ground apollonian ultra wideband fractal antenna and its backscattering

This paper presents the design of a modified ground apollonian ultra wideband (UWB) fractal antenna. The printed fractal antenna has been designed on a substrate with dielectric constant ?_r = 4.3 and thickness h = 1.53 mm. The antenna has been fabricated with optimized dimension and tested. The experimental result of this antenna exhibits UWB characteristics from frequency range 3 GHz to 18 GHz. This corresponds to 142.86% impedance bandwidth with center frequency of 10.5 GHz. The experimental radiation patterns of this antenna are nearly omni-directional in H-plane and bidirectional in E-plane. The effect of various design parameters on UWB characteristics have also been analyzed using a 3D electromagnetic simulator based on FEM method. The simulated and experimental results are in good agreement. The backscattering RCS of this UWB fractal antenna is better than ?31 dB throughout the FCC band (3.1 GHz to 10.6 GHz). The proposed coplanar waveguide feed appollian fractal antenna can be easily integrated with radio-frequency/microwave circuitry with low-manufacturing cost and useful for UWB applications.     

115 Gbit/s downstream and 10 Gbit/s upstream TWDM-PON together with 11.25 Gbit/s wireless signal utilizing OFDM-QAM modulation

In this work, we propose and investigate a 115 Gbit/s (4 × 28.75 Gbit/s) downstream and 10 Gbit/s upstream time- and wavelength-division-multiplexing passive optical network (TWDM-PON) together with 11.25 Gbit/s wireless broadcasting signal using multi-band orthogonal-frequency-division-multiplexing (OFDM) modulation within 10 GHz bandwidth. Here, to compensate the power fading and chromatic dispersion in the higher frequency, we utilize a −0.7 chirp parameter Mach–Zehnder modulator (MZM) for the OFDM signal. Hence, negative power penalties of −0.3 and −0.4 dB in the downstream and broadcasting wireless signals; and power penalty of 0.3 dB in the upstream signal are measured at the bit error rate (BER) of 3.8 × 10⁻³ after 20 km standard single mode fiber transmission without dispersion compensation.     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

Via-less CRLH-TL unit cells loaded compact and bandwidth-enhanced metamaterial based antennas

The via-less composite right hand left hand (CRLH)-TL unit cells loaded compact and bandwidth-enhanced metamaterial (MTM) antennas have been designed and experimentally investigated. Four novel unit cells are designed and its dispersion characteristics of the proposed unit cells are numerically calculated which follows CRLH-TL properties. Further, the conventional metallic vias of CRLH-TL have been eliminated to increase the fabrication flexibility. The four CRLH-TL unit cells are loaded into monopole antennas which result, four via-less open-ended MTM antennas respectively. Its ZOR (zeroth order resonance) bandwidth is increased by realizing small shunt capacitance and large shunt inductance. Further, to increase overall antenna bandwidth, merging of ZOR mode to the higher and lower order modes into a single pass band has been done by realizing proper CRLH-TL unit cells. The each proposed antenna has a dimension of 0.13λ₀ × 0.08λ₀ × 0.0085λ₀, where the free space wavelength λ₀ at 1.6 GHz. The four proposed antennas have S₁₁ < −10 dB fractional bandwidths (FBW) 173% (1–13.6 GHz), 169% (1.2–14.5 GHz), 158% (1.6–13.5 GHz) and 158% (1.6–13.5 GHz) respectively. The optimum gain and desired radiation characteristics have been obtained for all proposed antennas, which can be suitable for UWB applications. The CST-MWS has been used for the parametric study of the proposed antennas. A good agreement has been observed between simulated and experimental results.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.