A 1-V low power gain boosted self-cascoding current mirror operational transconductance amplifier

A low-voltage, micro-power, low-noise, high-gain, high-output swing current mirror-based operational transconductance amplifier (OTA) is presented. The proposed OTA achieves high DC gain and output swing by the adoption of gain boosted current mirroring and self-cascoding techniques. From the simulation, the proposed OTA implemented on a 0.18 μm CMOS shows the DC gain up to 90 dB with a gain bandwidth of 700 KHz for a load capacitor of 1 pF and an output voltage swing of 600 mV. The OTA dissipates only 750 nW from 1.0 V supply.     

The super-multi-tanh technique for bipolar linear transconductance amplifiers

A novel circuit design technique for bipolar linear transconductance amplifiers is presented. A triple-tail cell, which consists of three emitter-common transistors biased by a single tail current, is exchangeable with an emitter-coupled pair in the multi-tanh cell, such as a multi-tanh doublet, a multi-tanh triplet or a multi-tanh quad. Therefore, the multi-tanh technique is further theoretically expanded to the super-multi-tanh technique. In this paper, the super-multi-tanh technique is proposed and discussed, and furthermore, a super-multi-tanh doublet is verified with bipolar transistor-arrays and discrete resistors on a breadboard.     

A bulk-driven quasi-floating gate FVF current mirror for low voltage,low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.     

A floating generalized impedance converter with current feedback operational amplifiers

A novel generalized impedance converter topology realized using current feedback operational amplifiers is introduced in this paper. The main offered benefit, in comparison to the corresponding already published structure, is that frequency dependent negative resistors can now be also realized. Other benefits are the requirement for only grounded capacitors, the lower component count, and the capability of tuning through a grounded resistor. The correct operation of the proposed GIC has been verified through a design example, where a 3rd-order lowpass filter has been topologically simulated.     

A linear-high range output power control technique for cascode power amplifiers

In this paper a new linear power control technique is presented to control the output power of cascode power amplifiers. Using this technique the output power of power amplifier can be controlled from the maximum output power to −136 dBm, continuously. The characteristic of the output voltage versus control voltage is linear from −15.9 to 18.6 dBm (a range of 34.5 dB) of the output power. Also at this range the Amplitude Modulation to Phase Modulation (AM-PM) distortion is 43°. Furthermore, the input dynamic range is 0.373 V, which is less than the conventional techniques. Having a power controller in a low power path and a low input dynamic range leads to minimizing the controller dissipation and reduction of power added efficiency (PAE). The proposed technique is simulated using 0.13 μm CMOS process model using Advanced Design System and the results obtained are presented.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA.     

一个低功耗低电压的二级运放压摆率增强电路

本文提出了一个新颖的二级运放压摆率增强电路。该电路采用AB类输入级,提高了电流效率。相对于运放,它完全开环工作,因此不会影响运放的稳定性。当运放处于压摆阶段时,电路检测运放输入差分电压,产生外部的动态电流并注入运放,从而使加快负载电容的充/放电过程。电路仿真结果显示：对于大的输入阶跃信号,该电路可以减少50%的建立时间;将电路运用于采样保持电路时,该电路提高了无杂散动态范围44.6dB,降低了总谐波失真43.9dB。本文提出的电路非常适用于低电压（1.2V或更低）工作,并且只消耗200μA的静态电流。     

A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs

A pseudo-background continuous-time strategy is developed for gain and offset calibration in open-loop inter-stage residue amplifiers of pipeline ADCs. The ping-pong calibration strategy is enhanced for loop gain and accuracy to be utilized for open-loop RAs. Thanks to a reliable technique for preserving analog voltages for long time durations, data conversion continuously proceeds. In addition, other advantages of the foreground techniques, like lower power consumption and smaller area are achieved. The reduction in power consumption due to the elimination of a wide-bit digital processor easily overcomes the increase which stems from the replica residue amplifier. Storing the calibration results in reliable analog storages, the multiplexing frequency and clock frequency within the calibration loop are reduced to 100 KHz, respectively, which result in a significant amount of power reduction. Monte-Carlo analysis for 100 iterations shows that the calibration loop provides an absolute gain of 4 with the median value of 3.996 and standard deviation of 0.003, while the threshold voltages and reference levels experience a Gaussian distribution with 25 mV variations at 3σ. Total power consumption equals 1.8 mW for both the offset and gain calibration at 1.8 V (and 3.3 V for DAC) supply voltage. More than 9-bit accuracy is obtained at 50 mV peak-to-peak residue. Linearity is reduced to 7-bits for full-swing input range. Also, 13 dB and 8 dB improvement in SNDR and SFDR of a 13-bit 100S/s pipeline ADC is achieved when the offset and gain calibration loops are activated. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 μm CMOS technology.     

A new BICS for CMOS operational amplifiers by using oscillation test techniques

In this paper, we present a built-in current sensor to test operational amplifiers that takes advantage of previous results where the negative supply current has been taken as the test observable using the Oscillation-test technique. The sensor is applied to a variable-length chain of OTAs considering an exhaustive analysis of catastrophic defects (opens, shorts), Gate Oxide Short and Floating Gate defects. We analyse the sensitivity of both frequency and amplitude of the current consumption. Results show that the proposed sensor provides 97% fault coverage, as the previous results suggested.     

A current monitoring technique for IDDQ testing in digital integrated circuits

Although I_DDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this paper, a current monitoring technique that overcomes the current variations problem in I_DDQ testing is proposed. According to this, a core is partitioned into two subcircuits and the intrinsic leakage current of the one subcircuit is used to control the leakage current at the I_DDQ sensing node of the other and vice-versa during test application. This way process related leakage current variations are taken into account and small defective currents turn to be detectable according to the needs of modern nanometer technologies. Additionally, a Built-In Current Sensor is presented, which exploits the proposed technique and experimental results are illustrated by its application on a fabricated chip.     

A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC

In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required.     

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm². The obtained average reference current is 6 nA having a slope of 5.5pA/°C.     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.     

Energy efficient power allocation for co-located antenna systems with D2D communication

This paper investigates the energy efficient resource allocation when adding dedicated device-to-device (D2D) communication in the co-located antenna systems (CAS). We consider the user equipments (UEs) are changing over time and the appropriate potential UEs to form D2D pairs are varying with time. Our optimization objective is to maximize the system’s energy efficiency (EE) with the constraints of the maximum transmit power of UEs and D2D pairs in different total power consumption models. Firstly, an algorithm is developed to choose appropriate potential UEs to form D2D pairs in this paper. Then we exploit fractional programming method to obtain optimal energy efficient power allocation solutions. Simulation results are provided to demonstrate the effectiveness of the developed D2D pairs choosing algorithm and the power allocation algorithm.     

A new generation of modems for power efficient radio systems

A new class of generalized intersymbol-interference and jitter-free (GIJF) modulated signals is introduced. Computer simulation and hardware experimental research results demonstrate that our proposed new generation of signals and modulators leads to significant performance improvements in non-linearly amplified broadband radio systems. For increased power efficiency, non-linear amplification is required in most commercial satellite and terrestrial microwave systems. In particular, we demonstrate that the 3 dB envelope fluctuation of currently used offset raised-cosine overlapped QPSK systems is reduced to 0-5 dB, and that the BER performance is improved by approximately 1 dB. These significant technical performance advantages are expected to lead to more economical implementations of digital transmission systems.     

A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps

A simple dynamic biasing scheme to extend the input/output range of cascode amplifiers is introduced. It requires minimum extra hardware and no additional power consumption. A dynamic biased telescopic op-amp is discussed as an application example. Experimental results of a fabricated test chip in 0.5 μm CMOS technology are presented that verify the proposed technique.