Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

Multilevel characteristics for bipolar resistive random access memory based on hafnium doped SiO2 switching layer

We fabricated TiN/Hf:SiO₂/Pt memory cell with the small size of 1×1 um² by lithography and sputtering technology, which demonstrated excellent bipolar resistive switching (RS) characteristics. The device presents good endurance and outstanding uniformity. The coefficient of variation of V_set, V_reset, R_on and R_off were found to be 5.05%, 4.78%, 4.18%, and 15.78%, respectively. For the device with hafnium doped SiO₂ switching layer, multilevel storage capability can be successfully obtained by varying either the stop voltage or the compliance current in the SET process. In addition, the impact of forming current on the RS properties was studied. We found that the ratio of On/Off current for the device increased with the decrease of the forming current, which would be beneficial for the design of low power device. Possible RS mechanisms aiming to explain the impact of forming current on the RS characteristics and multilevel storage were also deduced.     

High-resolution transmission electron microscopy study on bipolar resistive switching behavior in TiO2 thin films

We fabricated TiO₂ thin films the by sol–gel process. Successful I–V curves can be obtained in the Cu/TiO₂/ATO structure device in which TiO₂ thin film was calcined at 300 °C. The bipolar resistive switching behavior was observed and the ratio of R_off/R_on can be increased to 10⁴. The switching voltage changes from 4.8 to 3.5 V when the current compliance drops from 10 to 0.1 mA. We also investigated the microstructure by HRTEM technology.     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Electrical properties of Π-conjugated Fe-TPP molecular solar cell device

A heterojunction device of Au/Fe-TPP/n-Si/Al was assembled by thermally evaporated deposition. The dark current density–voltage characteristics of device were investigated. Results showed a rectification behavior. Measurements of thermo electric power confirm that Fe-TPP thin film behaves as p-type semiconductors. Electronic parameters such as barrier height, diode ideality factor, series resistance, shunt resistance were found to be 0.83 eV, 1.5, 7 × 10⁵ Ω and 2 × 10¹⁰ Ω, respectively. The Au/Fe-TPP/n-Si/Al device indicates a photovoltaic behavior with an open circuit voltage V_oc of 0.52 V, short circuit current I_sc of 2.22 × 10^?6 A, fill factor FF of 0.49 and conversion efficiency 1.13% under white light illumination power 50 W/m².     

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/Al device

The dark current density–voltage characteristic of Au/ZnPc/Al device at room temperature has been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to be ohmic, while at high voltages, space charge limited the current mechanism dominated by exponential trapping levels. Junction parameters such as rectification ratio (RR), series resistance (R_s), and shunt resistance (R_sh) were found to be 9.42, 9.72 MΩ, and 0.88 × 10³ MΩ, respectively. The current density–voltage characteristics under white light illumination (100 W/m²) gives values of 0.55 V, 3 × 10⁻³ A/m², 0.18 and 5.8 × 10⁻⁴% for the open circuit voltage, V_oc, the short circuit current density (J_sc), the fill factor (FF), and conversion efficiency (η), respectively.     

The role of water in the device performance of n-type PTCDI-C8 organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C₈) organic field-effect transistors (OFETs). An aqueous solution process was applied to form the gelatin gate dielectric on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. The field-effect mobility in the saturation regime (μ_FE,sat) and the threshold voltage (V_T) values of a typical 40 nm PTCDI-C₈ OFET are (0.22 cm² V⁻¹ s⁻¹, 55 V) in vacuum and (0.74 cm² V⁻¹ s⁻¹, 2.6 V) in air ambient. The maximum voltage shift in hysteresis is also reduced from 10 V to 2 V when the operation environment for PTCDI-C₈ OFETs is changed from vacuum to air ambient. Nevertheless, a slight reduction of electron mobility was found when the device was stressed in the air ambient. The change in the device performance has been attributed to the charged ions generation owing to water absorption in gelatin in air ambient.     

A fundamental understanding of nickel oxide based resistive random access memory with high percentage of oxygen

In this paper, we report the fundamental properties of NiO_x based Resistive RAM (RRAM) devices with Al top electrode and Ni bottom electrode. The NiO_x deposition was performed in a relatively high oxygen environment. The initial J–V curves in positive and negative bias indicated symmetric behavior in spite of a significant difference in the vacuum work functions of Al and Ni. The capacitance–voltage characterizations indicated NiO_x to be a p-type semiconductor with acceptor doping density between 6 × 10¹⁸ cm^?3 and 5 × 10²⁰ cm^?3. Switching behavior was observed after electroforming the devices. The devices failed after multiple switching cycles by switching into a relatively low conductive state. The mechanism of failure was attributed to the formation of Al₂O₃ due to a slow oxidation of Al electrodes with repeated cycles.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Determination of the laterally homogeneous barrier height of palladium Schottky barrier diodes on n-Ge (1 1 1)

We have studied the experimental linear relationship between barrier heights and ideality factors for palladium (Pd) on bulk-grown (1 1 1) Sb-doped n-type germanium (Ge) metal-semiconductor structures with a doping density of about 2.5×10¹⁵ cm^?3. The Pd Schottky contacts were fabricated by vacuum resistive evaporation. The electrical analysis of the contacts was investigated by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements at a temperature of 296 K. The effective barrier heights from I–V characteristics varied from 0.492 to 0.550 eV, the ideality factor n varied from 1.140 to 1.950, and from reverse bias capacitance–voltage (C^?2–V) characteristics the barrier height varied from 0.427 to 0.509 eV. The lateral homogenous barrier height value of 0.558 eV for the contacts was obtained from the linear relationship between experimental barrier heights and ideality factors. Furthermore the experimental barrier height distribution obtained from I–V and (C^?2?V) characteristics were fitted by Gaussian distribution function, and their mean values were found to be 0.529 and 0.463 eV, respectively.     

Temperature-dependent resistive switching characteristics for Au/n-type CuAlOx/heavily doped p-type Si devices

Bipolar switching phenomenon is found for Au/n-type CuAlO_x/heavily doped p-type Si devices at temperatures above 220 K. For high or low resistive states (HRS or LRS), the electrical resistance is decreased with increasing temperature, indicating a semiconducting behavior. Carrier transport at LRS or HRS is dominated by hopping conduction. It is reasonable to conclude that the transition from HRS to LRS due to the migration of oxygen vacancies (V_O) is associated with electron hopping mediated through the V_O trap sites. The disappearance of the resistive switching behavior below 220 K is attributed to the immobile V_O traps. The deep understanding of conduction mechanism could help to control the device performance.     

In situ modification of low-cost Cu electrodes for high-performance low-voltage pentacene thin film transistors (TFTs)

We demonstrate low-voltage pentacene thin film transistors (TFTs) using in situ modified low-cost Cu (M-Cu) as source–drain (S/D) electrodes and solution-processed high capacitance (200 nF/cm²) gate dielectrics. Under a gate voltage of ?3 V, the device with M-Cu electrodes shows a much higher apparent mobility (1.0 cm²/V s), a positively shifted threshold voltage (?0.62 V), a lower contact resistance (0.11 MΩ) and a larger transconductance (12 μS) as compared to the device with conventional Au electrodes (corresponding parameters are 0.71 cm²/V s, ?1.44 V, 0.41 MΩ, and 5.7 μS, respectively). The enhancement in the device performance is attributed to the optimized interface properties between S/D electrodes and pentacene. Moreover, after encapsulation the M-Cu electrodes with a thin layer of Au in the aim of suppressing unfavorable surface oxidation, the electronic characteristics of the device are further improved, and highly enhanced apparent mobility (2.3 cm²/V s) and transconductance (19 μS) can be achieved arising from the increased conductivity of the electrode itself. Our study provides a simple and feasible approach to achieve high performance low-voltage OTFTs with low-cost S/D electrodes, which is desirable for large area applications.     

Characterization of MIS structures and thin film transistors using RF-sputtered HfO2/HIZO layers

MIS structures using HfO₂ and HIZO layers, both deposited by room temperature RF magnetron sputtering are fabricated for TFTs application and characterized using capacitance-voltage. The relative dielectric constant obtained at 1 kHz was 11, the charge carrier concentration of the HIZO was in the range of (2–3) × 10¹⁸ cm^− 3 and the interface trap density at flat band was smaller than 2 × 10¹² cm^− 2. The critical electric field of the HfO₂ layer was higher than 5 × 10⁵ V/cm, with a current density in the operating voltage range below 4 × 10^− 8 A/cm². The hysteresis and bias stress behavior of RF-sputtered HfO₂/HIZO MIS structures is presented. Fabricated HfO₂/HIZO TFTs worked in the operation voltage range below 8 V.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Determination of contact parameters of Ni/n-GaP Schottky contacts

The electrical analysis of Ni/n-GaP structure has been investigated by means of current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) measurements in the temperature range of 120–320 K in dark conditions. The forward bias I–V characteristics have been analyzed on the basis of standard thermionic emission (TE) theory and the characteristic parameters of the Schottky contacts (SCs) such as Schottky barrier height (SBH), ideality factor (n) and series resistance (R_s) have been determined from the I–V measurements. The experimental values of SBH and n for the device ranged from 1.01 eV and 1.27 (at 320 K) to 0.38 eV and 5.93 (at 120 K) for Ni/n-GaP diode, respectively. The interface states in the semiconductor bandgap and their relaxation time have been determined from the C–f characteristics. The interface state density N_ss has ranged from 2.08 × 10¹⁵ (eV^?1 m^?2) at 120 K to 2.7 × 10¹⁵ (eV^?1 m^?2) at 320 K. C_ss has increased with increasing temperature. The relaxation time has ranged from 4.7 × 10^?7 s at 120 K to 5.15 × 10^?7 s at 320 K.     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

Highly efficient green phosphorescent organic light emitting diodes with simple structure

A series of simple structures is investigated for realization of the highly efficient green phosphorescent organic light emitting diodes with relatively low voltage operation. All the devices were fabricated with mixed host system by using 1,1-bis[(di-4-tolylamino)phenyl]cyclohexane (TAPC) and 1,3,5-tri(p-pyrid-3-yl-phenyl)benzene (TpPyPB) which were known to be hole and electron type host materials due to their great hole and electron mobilities [μ_h(TAPC): 1 × 10^?2 cm²/V s and μ_e(TpPyPB): 7.9 × 10^?3 cm²/V s] [1]. The optimized device with thin TAPC (5–10 nm) as an anode buffer layer showed relatively high current and power efficiency with low roll-off characteristic up to 10,000 cd/m². The performances of the devices; with buffer layer were compared to those of simple devices with single layer and three layers. Very interestingly, the double layer device with TAPC buffer layer showed better current and power efficiency behavior compared to that of three layer device with both hole and electron buffer layers (TAPC, TpPyPB, respectively).     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.