Impact of elliptical cross-section on the propagation delay of multi-channel gate-all-around MOSFET based inverters

Multi-channel (MC) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the promising candidates for the next-generation high performance devices. However, due to fabrication imperfections the cross-section of GAA devices may be ellipse-shaped having different major (a) and minor (b) axes, instead of the theoretically ideal round shape. The aspect ratio (AR), defined as a/b, of such elliptical GAA devices can vary depending on a and b. This introduces variability in the effective diameter, which in turn affect the performance parameters of circuits based on elliptical GAA MOSFETs. In the present work we have investigated the impact of diameter variability on the transient response of MC elliptical GAA MOSFET based CMOS inverters with a novel perspective. We have modeled the spread in the effective diameter by a parameter, σ, the standard deviation (SD), which may be thought of as a quantitative measure of the amount of variability introduced in the device. We have elaborated the ‘ON-Resistance’ method for calculating the propagation delay of MC GAA MOSFET based CMOS inverters. Computations were carried out to show the dependence of the propagation delay of such inverters on some important device/circuit parameters. We have also shown that even long channel elliptical devices can offer significant reduction of circuit delay (comparable to short channel devices) by proper tuning the effective diameter and number of channels, provided the admissible small dimensional effects have been taken into account.     

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain–frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.     

DC and analog/RF performance optimisation of source pocket dual work function TFET

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n⁺ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.     

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

This paper investigates and compares the impacts of metal-gate work-function variation on important analog figures-of-merit (FOMs) for TFET and FinFET devices using 3-D atomistic TCAD simulations. Our study indicates that, at 0.6 V supply voltage and 0.2 V gate-voltage overdrive, TFET exhibits superior variation immunity regarding transconductance to drain–current ratio (g_m/I_DS), output resistance (R_out) and intrinsic gain, and comparable variability in g_m and cutoff frequency (f_T) as compared with the FinFET counterparts. In addition, how the correlations between pertinent parameters (e.g., g_m and R_out) impact the variation immunity of important analog FOMs are analyzed. Our study may provide insights for low-voltage analog design using TFET/FinFET technologies.     

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.     

Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability

In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600 K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (I_ds) and other for cut-off frequency (f_T) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65 V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of I_on/I_off, Subthreshold Swing (SS), device efficiency, f_T, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.     

Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET

A two-dimensional analytical model for fully depleted cylindrical/surrounding gate MOSFET is presented. We used the evanescent mode analysis to solve the 2D Poisson's equation and to deduce analytically the surface potential and threshold voltage expressions of this device. Comparison with the other models reveals a good agreement.     

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (g_m), output conductance (g_d), early voltage (V_EA), intrinsic gain (A_V), trans-conductance generation factor (TGF), cut-off frequency (f_T), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.     

Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (t_oxh) and channel length (L_g) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in t_oxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

A Joint Scheme of AGC and Gain/Phase Mismatch Compensation for QPSK DCR

This paper presents a simple gain/phase blind compensation algorithm with an automatic gain control (AGC) function for the adoption of the AGC function and compensation for gain/phase imbalances in quadrature phase shift keying (QPSK) direct conversion receivers (DCRs). The AGC function is interactively operated with the compensation algorithm for gain/phase imbalances. By detecting the gain sum and difference values between the I‐channel and Q‐channel, the combined AGC and gain imbalance compensation algorithm provides a simpler DCR architecture.     

射频功率HBT热稳定性的一种新表征方法

从热电反馈网络角度出发,在考虑到晶体管发射极电流随温度的变化、发射结价带不连续性（△Ev）、重掺杂禁带变窄（△Eg）及基极和发射极加入镇流电阻（RB和RE）等情况下,首次较全面地给出了功率晶体管热稳定因子S表达式。用该表达式可以很方便、明了地对功率双极晶体管进行热稳定性分析。分析了镇流电阻对射频功率晶体管安全工作区以及S的影响。结果表明,功率异质结双极晶体管（HBT）热稳定性优于同质结双极晶体管（BJT）,适当选取RB和RE可使S=0,使由器件本身产生的耗散功率而引起的自加热效应被完全补偿,器件特性得以保持,不因自热而产生漂移,这是同质结器件所无法实现的。     

不对称半桥变换器的小信号建模与仿真研究

不对称半桥变换器利用自身的寄生器件实现了开关管的零电压操作,在不影响电路整体结构,以及不增加成本的前提下达到了很好的输入、输出特性。文章建立了该类变换器的小信号模型,进行了动态分析、仿真研究及补偿回路设计,并对整体的电路稳定性和几个关键的频率特性进行了研究。     

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25–125 °C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. Different degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what effectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 °C using inverter and pass transistor operations in a 0.35 μm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation.     

Experimental realization of 40 Gbit/s single-to-single and single-to-dual channel wavelength conversions in LiNbO3 waveguides with two-pump configuration

An all-optical 40 Gbit/s tunable single-tosingle channel wavelength conversion is experimentally realized based on cascaded sum- and difference-frequency generation (cSFG/DFG) in periodically poled LiNbO3 (PPLN) waveguides. By employing two tunable filters to effectively suppress the amplified spontaneous emission (ASE) noise, both wavelength down- and upconversions are simultaneously observed. We also propose and verify a novel cSFG/DFG-based single-todual channel wavelength conversion by setting two pumps (pumpl, pump2) close to each other or pump2 and the signal close to each other. For the latter, two kinds of cSFG/DFG schemes are both demonstrated The dependence of the conversion efficiencies of two channel idler waves on pumpl wavelength is discussed.The wavelength relationships between two channel idler waves and the three incident waves are investigated in detail theoretically as well as experimentally.     

啁啾光纤光栅EDFA增益平坦滤波器的设计与制作

采用啁啾相位掩膜板和程控扫描曝光技术,在经过载氢增敏处理的普通单模光纤上制作出可以用于掺铒光纤放大器(EDFA)增益谱平坦化的啁啾光纤布喇格光栅(CFBG)型增益平坦滤波器(GFF),运用数值解析的方法得到曝光量曲线,并将之分解成曝光频率、曝光功率密度、光斑尺寸和光纤移动速度的曝光函数,按照曝光函数进行程控扫描曝光从而精确控制光栅的反射率.对制作的CFBG进行退火老化处理和温度补偿及保护封装,封装后GFF的温漂系数在-20～ 70 ℃内变化小于1 pm/℃,经平坦后的EDFA增益谱在30 nm带宽范围内,不平坦度＜±0.3 dB.根据不同的EDFA的ASE谱,可程控给出不同的曝光函数,以制作具有不同反射谱的CFBG型GFF.     

RF, DC, and reliability characteristics of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for Si RF IC applications

High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF//spl mu/m/sup 2/) up to 20 GHz, low leakage current of 4.9/spl times/10/sup -8/ A/cm/sup 2/ at 2 V and 125/spl deg/C, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (/spl alpha/) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.     

Analysis and design of joint CFO/channel estimate techniques for a cooperative STBC‐OFDM system

This paper studies the joint estimation technique of carrier frequency offset (CFO) and channel information for a distributed decode‐and‐forward (DF) cooperative space‐time block‐coded (STBC) orthogonal frequency division multiplexing (OFDM) system. For the considered relay system, we provide theoretical analysis of the effects upon the output signal‐to‐noise ratio (SNR), which is caused by the CFO/channel estimation error. Based on the provided analytical results, a joint CFO/channel estimation scheme is then developed, where the CFO estimate is achieved by a multiple‐dimensional linear search algorithm. Furthermore, we propose an alternative estimation solution with iteration approach being designed for the CFO estimation prior to the channel estimation. In contrast to the former estimator, the iterative method enjoys the advantage of the substantially reduced implementation complexity without sacrificing the estimate performance. The conducted computer simulation results verify the effectiveness of the proposed schemes.