A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing

A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point \((IIP_{3})\) of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high \(IIP_{3}\) by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and \(S_{11}\) at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept \((IIP_{3})\) of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.     

18‐31 GHz GaN wideband low noise amplifier (LNA) using a 0.1 μm T‐gate high electron mobility transistor (HEMT) process

GaN technology has attracted main attention towards its application to high‐power amplifier. Most recently, noise performance of GaN device has also won acceptance. Compared with GaAs low noise amplifier (LNA), GaN LNA has a unique superiority on power handling. In this work, we report a wideband Silicon‐substrate GaN MMIC LNA operating in 18‐31 GHz frequency range using a commercial 0.1 μm T‐Gate high electron mobility transistor process (OMMIC D01GH). The GaN MMIC LNA has an average noise figure of 1.43 dB over the band and a minimum value of 1.27 dB at 23.2 GHz, which can compete with GaAs and InP MMIC LNA. The small‐signal gain is between 22 and 25 dB across the band, the input and output return losses of the MMIC are less than ?10 dB. The P_1dB and OIP3 are at 17 dBm and 28 dBm level. The four‐stage MMIC is 2.3 × 1.0 mm² in area and consumes 280 mW DC power. Compared with GaAs and InP LNA, the GaN MMIC LNA in this work exhibits a comparative noise figure with higher linearity and power handling ability.     

一种0.8GHz～6GHz CMOS超宽带低噪声放大器设计

给出了一个针对0.8GHz～6GHz 的超宽带低噪声放大器 UWB LNA(ultra-wideband low noiseamplifier)设计。设计采用0.18μm RF CMOS 工艺完成。在0.8GHz～6GHz 的频段内,放大器增益 S21达到了17.6dB～13.6dB。输入、输出均实现良好的阻抗匹配,S11、S22均低于-10dB。噪声系数(NF)为2.7dB～4.6dB。在1.8V 工作电压下放大器的直流功耗约为12mW。     

一种超宽带低噪声放大器

提出一个共源共栅结构的超宽带低噪声放大器。该电路基于台积电0.18μmCMOS工艺,工作在3GHz～5GHz频率下,用来实现超宽带无线电。仿真结果表明,该低噪声放大器有最大13.6dB的增益。整个频段噪声系数小于1.9dB。输入和输出反射损耗都小于-11dB。一阶压缩点在-15dBm左右。功耗为18.7mW。     

DC到2.6GHz硅基MMIC放大器

本文采用基于硅基的：BiCMOS工艺设计制作了一款带宽为DC到2．6GHZ的低噪声、高增益MMIC放大器。该放大器为了实现从DC到2．6GHz的带宽，保证有足够的增益和理想的增益平坦度，采用了负反馈结构，两级级联，并选用了一种结构新颖的微波晶体管。该放大器具有功率增益高、频带较宽、噪声系数较小的特点。在仿真过程中其3dB带宽约3GHz，增益为26．6dB(1．5GHz时)，1dB压缩点输出功率约为1dBm；样品的实测结果为3dB带宽约2．6GHz，增益为26dB(1．5GHz时)，1dB压缩点输出功率约为1dBm。     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...     

应用于北斗卫星通信系统的低噪声放大器设计

北斗卫星导航系统由我国自主研发,其研制目的是为了在日益严峻的世界环境下巩固我国的军事实力。北斗射频接收芯片是北斗卫星导航系统中整个地面端设备的核心,因此,关于射频接收机芯片的研发工作具有十分重要且实际的意义。文中在基于窄带低噪声放大器理论的基础上,采用TSMC0．18μmCMOS工艺设计了一种应用于北斗通信系统中的低噪声放大器。放大器采用改进的单转双电路结构,并通过缓冲级电路对差分信号的幅度和相位偏差进行了有效的校正。实验结果表明该电路在2．45GHz-2．55GHz频带内输入回波损耗小于-28dB,噪声系数小于1．1dB,功率增益大于15dB,电压增益高于32dB。     

采用噪声抵消技术的高增益CMOS宽带LNA设计

设计了一种面向多频段应用的CMOS宽带低噪声放大器。采用噪声抵消技术以及局部负反馈结构,引入栅极电感补偿高频的增益损失,电路具有高增益、低噪声的特点,并且具有平坦的通带增益。设计采用UMC 0.18μm工艺,后仿真显示:在1.8 V供电电压下,LNA的直流功耗约为9.45 mW,电路的最大增益约为23 dB,3 dB频带范围为0.1 GHz¹.35 GHz,3 dB带宽内的噪声约为1.7 dB1.35 GHz,3 dB带宽内的噪声约为1.7 dB⁵ dB;在1 V供电电压下,电路依然能够保持较高的性能。     

基于噪声消除技术的超宽带CMOS低噪声放大器设计

为满足3.5 GHz单载波超宽带无线接收机的射频需求,设计了一种工作在3～4 GHz的超宽带低噪声放大器。电路采用差分输入的CMOS共栅级结构,利用MOS管跨导实现宽带输入匹配,利用电容交叉耦合结构和噪声消除技术降低噪声系数,同时提高电压增益。分析了该电路的设计原理和噪声系数,并在基于SMIC 0.18μm CMOS射频工艺进行了设计仿真。仿真结果表明:在3～4GHz频段内,S11和S22均小于-10 dB,S21大于14dB,带内起伏小于0.5dB,噪声系数小于3dB;1.8V电源电压下,静态功耗7.8mW。满足超宽带无线接收机技术指标。     

Survey on parameter optimization of mobile communication band low noise amplifier design

A comparative study on recent works on low noise amplifiers (LNAs) designed to be operated at mobile communication band is performed in this article. Here, specifications of different generations of mobile communication are listed, which are considered to classify recent works on LNAs. Even though gain and noise figure (NF) are the primary parameters of LNA; other parameters like power, linearity, bandwidth, and area also get importance. Due to this, optimization techniques handpicked for all those parameters are discussed. The inverse relation between gain and NF is exploited to achieve low noise and high gain together. While increasing the gain, power consumption is increased by drain current. Each LNA is found as good in terms of gain and other parameters to satisfy the requirements. The figure of merit is opted to find the performance of each LNA, and the comparison is performed. The best parameters reported in the comparison are 31.53 dB of gain, 0.7 dB of NF, 0.03 mw of power consumption, 18.14 dBm of third‐order input intercept point (IIP3), 24 GHz bandwidth and 0.0052 mm² of area at different frequencies and technology nodes. In this survey, as per the optimized FoM for mobile communication, cross‐coupled common gate differential LNA, which was designed to be operated at 0.3 to 2.96 GHz gives better results among CMOS LNAs.     

低功耗低噪声CMOS放大器设计与优化

分析了两种传统的基于共源共栅结构的低噪声放大器LNA技术:实现噪声优化和输入匹配SNIM技术并在功耗约束下同时实现噪声优化和输入匹配PCSNIM技术。针对其固有不足,提出了一种新的低功耗、低噪声放大器设计方法。     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

一种新型负反馈超宽带低噪声放大器的设计与实现

随着超宽带技术的发展,系统设计对低噪声放大器的性能提出了越来越高的要求。针对宽带放大器增益平坦度低。匹配性差等问题,本文从负反馈理论着手,改进了负反馈网络。通过ADS软件的辅助设计,实现了30MH—1．35GHz频段下的低噪声放大器的设计。通过对各项电路参数的优化,实现了增益为17．7dB,增益平坦度小于dB,输入输出电压驻波比小于1．5,噪声系数小于2．6的技术指标。     

A W‐band RF‐MEMS switched LNA in a 70 nm mHEMT process

This work presents a monolithic integrated reconfigurable active circuit consisting of a W‐band RF micro‐electro‐mechanical‐systems (MEMS) Dicke switch network and a wideband low‐noise amplifier (LNA) realized in a 70 nm gallium arsenide (GaAs) metamorphic high electron mobility transistor process technology. The RF‐MEMS LNA has a measured gain of 10.2–15.6 dB and 1.3–8.2 dB at 79–96 GHz when the Dicke switch is switched ON and OFF, respectively. Compared with the three‐stage LNA used in this design the measured in‐band noise figure (NF) of MEMS switched LNA is minimum 1.6 dB higher. To the authors’ knowledge, the experimental results represent a first time demonstration of a W‐band MEMS switched LNA monolithic microwave integrated circuit (MMIC) in a GaAs foundry process with a minimum NF of 5 dB. The proposed novel integration of such MEMS switched MMICs can enable more cost‐effective ways to realize high‐performance single‐chip mm‐wave reconfigurable radiometer front‐ends for space and security applications, for example. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:639–646, 2015.     

一种射频CMOS低噪声放大器的设计

应用TSMC0.35um CMOS工艺模型,设计了可应用于无线通信系统的低噪声放大器(LNA),电路采用单端共源共栅结构,用SmartSpice对电路进行分析优化,仿真结果表明,噪声系数为1.65dB,增益高于20dB。     

A broadband hybrid GaN cascode low noise amplifier for WiMax applications

This article reports a Microstrip design for low noise amplifier (LNA) using a packaged commercial GaN‐on‐SiC high electron mobility transistor (HEMT). A cascode configuration with an inter‐stage matching and an independent biasing technique was used. A lumped elements design was first developed, analyzed, and simulated in ADS. Then the design was implemented using microstrip technology and simulated using the momentum EM simulation in ADS. The LNA is easy to fabricate, has a low cost, and can be easily modified for other applications. The proposed GaN LNA showed a gain of 13.5 dB with a noise figure (NF) of 3 dB from 2.8 to 3.8 GHz.     

5.2GHz CMOS功率放大器设计

采用TSMC0.18μmCMOS工艺设计了一个5.2GHzWLAN(无线局域网)的功率放大器,该放大器采用两级差分结构。为了提高其线性度和功率附加效率,在每个差分放大级共源共栅电路之间引入电感,以及在每一级共源共栅放大器内部引入了多个MOS管的串并联。在ADS2009软件平台下对该功率放大器进行仿真,并应用Cadence软件进行功率放大器电路的版图设计。仿真结果表明,在1.8V工作电压下,1dB压缩点输出功率为19.6dBm,增益为28.2dB,功率附加效率为18.1%,符合无线局域网802.11a标准系统的要求。     

A class-E power amplifier with high efficiency and high power-gain for wireless sensor network

In the literature, a number of two-stage class-E power amplifiers have been reported for wireless sensor network (WSN) applications. However, they suffer from the requirement of larger silicon area, inductors with high quality factor, large number of off-chip decoupling capacitors, high input power, voltage stress handling capability and efficiency degradation due to finite on-resistance and surplus capacitance of switching transistors. In order to overcome these limitations and to enhance the power added efficiency, two novel two-stage class-E power amplifiers denoted as PA1 and PA2 are proposed in this paper. Both the amplifiers use a driver amplifier with capacitive feedback and pi-matching at the input. PA1 uses a main amplifier with negative-capacitance cascode topology. PA2 uses a diode connected NMOS auxiliary transistor with RC source degeneration in the driver amplifier, negative-capacitance cascode configuration with a parallel LC-tuning circuit in the main amplifier. To evaluate the efficacy of these circuits, the proposed power amplifiers are implemented in UMC 0.18-µm standard RFCMOS process with the supply voltage of 3.0 V and the operating frequency of 2.45 GHz and studied through post-layout simulation using Cadence Virtuoso (IC616) Analog Design Environment. From this study, it is found that the proposed power amplifiers have the power added efficiency of (45.02 %, 54.87 %), the saturated output power at 1-dB compression point (P1-dB) of (21.52 dBm, 23.17 dBm), the power gain of (27.29 dB, 28.74 dB) and the output referred intercept point (OIP3) of (19.41 dBm, 22.67 dBm), respectively. Both of these power amplifiers have higher figure of merit (FoM) of (53.80, 57.98) when compared to other reported works. It is observed that the proposed power amplifiers are suitable to operate under low input power of -8 dBm and hence it meets the requirement of WSN applications.

     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.