A Low-Noise GaAs Monolithic Broad-Band Amplifier Using a Drain Current Saving Technique (Short Paper)

A low-noise and low-power GaAs monolithic broad-band amplifier is proposed and has been developed, which has a new cascade connection with a large gate-width input FET and the other circuits in such a way that the output stage current flows through the input FET. The fabricated amplifier operates on +5-V single supply voltage, and provides a 3.3-dB noise figure, less than 180-mW power dissipation, and a 10-MHz--2.0-GHz bandwidth with 16-dB gain.     

Design and Performance of Monolithic GaAs Direct-Coupled Preamplifiers and Main Amplifiers

The design and performance of a GaAs direct-coupled preamplifier and main amplifier is described. The amplifiers are fabricated by the self-aligned implantation for n/sup +/ -Iayer technology (SAINT) process. The developed preamplifiers have 13-dB gain, 3-GHz bandwidth, and 4.8-dB noise figure for the one-stage amplifier, and 22-dB gain, 2.7-GHz bandwidth, and 5.6-dB noise figure for the two-stage amplifier. The developed four-stage main amplifier has 36-dB gain and 1.5-GHz bandwidth with a power consumption of 710 mW. These amplifiers are promising candidates for application to high-speed data communication systems.     

GaAs Monolithic Low-Power Amplifiers with RC Parallel Feedback (Short Paper)

GaAs monolithic broad-band low-power-dissipated amplifiers with inductive/resistive load and RC parallel feedback circuits have been developed. An inductive load amplifier provides a gain of 8 dB, a 3-dB bandwidth of 2.5 GHz, and a noise figure of 2.7 dB at 1 GHz with less than + 1-V supply voltage and very low-power dissipation of 20 mW. A resistive load two-stage amplifier provides a gain of 15 dB and a 3-dB bandwidth of 2 GHz. Input and output reflection coefficients at 1 GHz are -13 dB and -21 dB, respectively.     

12-GHz-Band Low-Noise GaAs Monolithic Amplifiers

One- and two-stage 12-GHz-band low-noise GaAs monolithic amplifiers have been developed for use in direct broadcasting satellite (DBS) receivers. The one-stage amplifier provides a less than 2.5-dB noise figure with more than 9.5-dB associated gain in the 11.7-12.7-GHz band. In the same frequency band, the two-stage amplifier has a less tlhan 2.8-dB noise figure with more than 16-dB associated gain. A 0.5-µm gate closely spaced electrode FET with an ion-implanted active layer is employed in the amplifier in order to achieve a low-noise figure without reducing reproducibility. The chip size is 1 mm x 0.9 mm for the one-stage amplifier, and 1.5 mm x 0.9 mm for the two-stage amplifier.     

Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.     

A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth

A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and /spl sim/5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP/sub 1 dB/ and IIP/sub 3/ are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.     

Ultra-Broad-Band GaAs Monolithic Amplifier

GaAs monolithic IC design and fabrication techniques suitable for baseband pulse amplification have been developed. The developed GaAs monolithic amplifier has a two-stage construction using two source-grounded FET's. To reduce input VSWR without serious noise-figure degradation, an inter-gate-drain negative feedback circuit was adopted. An interstage circuit is a dc-coupled circuit consisting of an appropriate impedance transmission line. Gate voltage for the second-stage FET is self-biased. The amplifier has 13.5-dB gain over the 3-dB bandwidth from below 500 MHz to 2.8 GHz. Less than 6-dB (7-dB) noise figure was obtained from 700 MHz to 2.2 GHz (150 MHz to 3 GHz). Input VSWR is less than 1.5     

Ultra-broad-band GaAs monolithic amplifier

GaAs monolithic IC design and fabrication techniques suitable for baseband pulse amplification have been developed. The developed GaAs monolithic amplifier has a two-stage construction using two source-grounded FET's. To reduce input VSWR without serious noise-figure degradation, an inter-gate-drain negative feedback circuit was adopted. An interstage circuit is a dc-coupled circuit consisting of an appropriate impedance transmission line. Gate voltage for the second-stage FET is self-biased. The amplifier has 13.5-dB gain over the 3-dB bandwidth from below 500 kHz to 2.8 GHz. Less than 6-dB (7-dB) noise figure was obtained from 700 MHz to 2.2 GHz (150 MHz to 3 GHz). Input VSWR is less than 1.5     

Ultra-broad-band GaAs monolithic direct-coupled feedback amplifiers

GaAs monolithic direct-coupled amplifiers with load resistor and feedback resistor have been developed. The fabricated amplifier using the self-aligned implantation for n⁺-layer technology (SAINT) FET's has a 10-dB gain, a 7.2-dB noise figure, and input VSWR less than 2.0 over the frequency range from dc to 4 GHz.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

毫米波大动态宽带单片低噪声放大器

利用0.25μmGaAsPHEMT低噪声工艺,设计并制造了2种毫米波大动态宽带单片低噪声放大器。第1种为低增益大动态低噪声放大器,单电源+5V工作,测得在26～40GHz范围内,增益G=10±0.5dB,噪声系数NF≤2.2dB,1分贝压缩点输出功率P1dB≥15dBm;第2种为低压大动态低噪声放大器,工作电压为3.6V,静态电流0.6A(输出功率饱和时,动态直流电流约为0.9A),在28～35GHz范围内,测得增益G=14～17dB,噪声系数约4.0dB,1分贝压缩点输出功率P1dB≥24.5dBm,最大饱和输出功率≥26.8dBm,附加效率约10%～13.6%。结果中还给出了2种放大器直接级联的情况。     

Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f/sub t/ and f/sub max/ larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V/sub pp/ limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 V/sub pp/) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible.     

一种S波段平衡式限幅低噪声放大器的设计

介绍了一种小型化平衡式限幅低噪声放大器。该放大器采用Lange桥平衡结构,在实现低噪声的同时,保证了小电压驻波比;在3.0～3.5GHz频带内,噪声系数小于1.3dB,输入输出驻波系数小于1.3,增益大于27dB,平坦度±0.6dB以内,输出1dB压缩点大于12dBm。该放大器能够承受最大5W的连续波功率输入,且大功率输入时的驻波系数小于1.3。     

11.GHz GaAs Power MESFET Load-Pull Measurements Utilizing a New Method of Determining Tuner Y Parameters

A Ioad-pull technique utilizing a new method of determining tuner Y parameters is proposed for huge-signal characterization of microwave power transistors. Large-signal input-output transfer characteristics of an active circuit containing a GaAs FET and an input matching circuit are measured by inserting a microstrip tuner between the active circuit output drain terminal and the 50-Omega load. The microstrip-tuner Y parameters are determined by comparing the dc bias-dependent small-signal S parameter S/sub 22/ of the active circuit and that of the circuit which contains the active circuit and microstrip tuner. The reflection coefficient presented to the active circuit output drain terminal is derived from tuner Y parameters. Optimal load impedances for output power, obtained with this new Ioad-pull technique, are used to design X-band GaAs FET power amplifiers. An 11-GHz power amplifier with a 3000-mu m gate-width FET chip delivers 1-W microwave power output with 4-dB gain in the 500-MHz band.     

Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier

We present the design of two wide-band, low-power and low-noise amplifiers (LNAs) using SiGe BiCMOS technology. The distributed LNA demonstrated 0.1-23-GHz bandwidth and 14.5-dB gain with less than /spl plusmn/1-dB gain flatness. It exhibited 5-dB noise figure and 14.8-dBm output IP3, and dissipated 54-mW dc power. Comparable circuit performance was also obtained in the lumped LNA while utilizing only one-fifth the chip area of the distributed LNA.     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

44-GHz monolithic GaAs FET amplifier

Millimeter-wave monolithic GaAs FET amplifiers have been developed. These amplifiers were fabricated using FET's with MBE-grown active layers and electron-beam defined sub-half-micrometer gates. Source groundings are provided through very low inductance via holes. The single-stage amplifier has achieved over a 10-dB gain at 44 GHz. A 300-µm gate-width amplifier has achieved an output power of 60 mW with a power density of 0.2 W per millimeter of gate width.     

Application of enhancement mode FET technology for wirelesssubscriber transmit/receive circuits

Single-supply power amplifiers have become the new paradigm in portable phone handsets due to the recent availability of heterojunction bipolar transistor (HBT) and pseudo enhancement mode PHEMT technology. We have developed a true enhancement mode heterostructure insulated-gate FET device (HIGFET) which is suitable for use in both saturated and linear power amplifiers. A three-stage power amplifier designed for 1900-MHz NADC application delivered +30-dBm output power and 41.7% power-added efficiency with an adjacent channel power of -29.8 dBc and alternate adjacent channel power of -48.4 dBc. In addition to this, we have demonstrated excellent noise figure and linearity performance for small-signal applications. At 900 MHz and bias conditions V_DS=1.0 V and I_DSQ=1 mA, a single-stage amplifier achieved a noise figure of 1.17 dB with an associated gain of 18.5 dB. These results make the technology an ideal candidate for application in both transmitter and receiver circuits     

GaAs converter IC's for C-band DBS receivers

GaAs downconverter Monolithic Microwave Integrated Circuits (MMICs) for use in C-band direct broadcast satellite (DBS) receivers were developed. The IC consists of four (4) RF functional blocks and a dc bias block. The RF section includes a low noise amplifier, IF amplifier, mixer, and local oscillator. The dc section incorporates an internal dc bias generation circuit to compensate for device parameter fluctuations in wafer processing. The IC makes it easy to design a complete out-door converter unit with only the addition of two low noise FETs, a band pass filter, and an external dielectric resonator. This IC is realized on a small chip of only 1.1 mm×1.6 mm. The gate length of the FET is 0.5 μm. The active layers of the FETs and resistors are formed by an ion-implantation technique. This IC has a 3.0-dB noise figure and a 43-dB conversion gain at 80-mA total current consumption. To realize compact size and low cost, these ICs are offered in 12-pin QFP plastic packages