Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors

In this paper, low-frequency noise (LFN) in N- and P-channel dynamic-threshold (DT) MOSFETs on Unibond substrate (SOI) is thoroughly investigated and, especially, an improved formulation of classical McWhorter’s noise model is proposed. In order to confirm our approach, an experimental comparison between body tied and DTMOS on SOI substrate has been achieved in terms of LFN behaviour. Furthermore, two different types of DTMOS transistors have been used: with and without current limiter. The LFN in DTMOS is analysed in ohmic and saturation regimes and the impact of the use of a current limiter (clamping transistor) is thoroughly analysed. An explanation based on floating body effect inducing excess noise is also proposed.     

Impact of preanneal process on threshold voltage of MOS transistors for trench DRAM

As the first step of DRAM manufacture, preanneal process plays an important role in determining the threshold voltage variation. It is found that the higher trans-1,2-dichloroethene flow in pad oxide growth and the higher nitrogen flow in high-temperature annealing step would respectively engender a lower boron segregation coefficient and higher nitridation of the oxide, both modify the boron distribution in the substrate and consequently the behavior of the threshold voltage. As the feature size of DRAM devices enter nanometer regime, besides gate oxidation, ion implantation and related thermal processes, the impact of preanneal process condition should be prudentially taken into consideration for rigorous control of the threshold voltage in the advanced DRAM production.     

Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors

The design of junction isolated DMOS transistors suitable for monolithic integration has been studied. The purpose of this correspondence is to describe one of the key tradeoffs when designing these devices for high breakdown voltages (200 V for our example). It is a tradeoff primarily between threshold voltage and the punchthrough voltage of the channel diffusion, however, the avalanche breakdown voltage, on-resistance, and source-to-substrate punchthrough voltage are also affected. As an example, the design of a device for 200-V operation is described. The discussion is, however, general and can be applied to other DMOS designs as well.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Temperature dependence of apparent threshold voltage of silicon MOS transistors at cryogenic temperatures

Measurements of apparent threshold voltages for conduction of bothn-p-nandp-n-pMOS-     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

硅化物阻挡层对高压漏扩展MOS晶体管的影响

Silicide-block-film effects on drain-extended MOS （DEMOS） transistors were comparatively investigated, by means of different film stack stoichiometric SiO2 and silicon-rich oxide （SRO）. The electrical properties of the as-deposited films were evaluated by extracting source/drain series resistance. It was found that the block film plays a role like a field plate, which has significant influence on the electric field beneath. Similar to hot-carrier- injection （HCI） induced degradation for devices, the block film initially charged in fabrication process also strongly affects the device characteristics and limits the safe operating area.     

Silicide-block-film effects on high voltage drain-extended MOS transistors

Silicide-block-film effects on drain-extended MOS (DEMOS) transistors were comparatively investi-gated, by means of different film stack stoichiometric SiO2 and silicon-rich oxide (SRO). The electrical properties of the as-deposited films were evaluated by extracting source/drain series resistance. It was found that the block film plays a role like a field plate, which has significant influence on the electric field beneath. Similar to hot-cartier-injection (HCI) induced degradation for devices, the block film initially charged in fabrication process also strongly affects the device characteristics and limits the safe operating area.     

An efficient method for determining threshold voltage, seriesresistance and effective geometry of MOS transistors

An accurate and robust method of extracting the threshold voltage, the series resistance and the effective geometry of MOS transistors is presented. The method is based on efficient nonlinear optimization using an iterative linear regression procedure which usually converges in less than four rounds. Thereby extracted parameters are obtained from analytical expressions for the solutions to a linear system of equations whereby time consuming numerical differentiations are avoided. MOSFET parameters are explicitly identified as parameters of an underlying widely used device model that is a good approximation for operation in the linear region. The method is particularly suitable for process characterization and can be used on as few as twelve data points (three data points from each of four different size transistors). By connecting external resistors in series with the transistors, we show that the extracted values of the parameters are independent of the series resistance     

Improvement of SOI MOS current-mirror performances usingserial-parallel association of transistors

The serial-parallel association of SOI MOSFETs proves to be useful for increasing the breakdown voltage and the early voltage of transistor structures. This permits one to realise current mirrors with an output-to-input current ratio close to unity in the weak, moderate and strong inversion regimes of the MOSFETs     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

Peculiarities of three-dimensional simulation of SOI MOS transistors with an indirect gate

A methodology for a three-dimensional (3D) simulation of submicron SOI MOS transistors, taking into account a lithographic topology distortion, is presented. The peculiarities of constructing a 3D structure are considered. An efficient method for grid generation is proposed. The results of simulating O-type SOI MOS transistors with and without precorrection of topology are given.     

Measurement of threshold voltages of thin-film accumulation-modePMOS/SOI transistors

Accumulation-mode PMOS transistors on SOI (silicon on insulator) are characterized by several conduction mechanisms. Measurements of the threshold voltage corresponding to each of them are presented for the first time. An intuitive physical interpretation of their dependence on the front- and back-gate voltages is also given     

New method of determination of the flat-band voltage in SOI MOS structures

A new method to determine the flat-band voltage V_FB in a MOS structure has been proposed. It is based on measuring a voltage which corresponds to a capacitance equal to 0.9 of the oxide capacitance. The method is especially suited for SOI (silicon on insulator) structures, but could be useful in conventional types. In the latter case the error of determination of V_FB caused by an uncertainty in doping concentration is smaller than in the classical procedure, especially when the thickness of the dielectric is small.     

Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors

The subthreshold radio-frequency (RF) characteristics of multi-finger nanoscale MOS transistors were studied by using the measured scattering (s) parameters. Small-signal circuit parameters were determined based on a simplified small-signal equivalent circuit model. We found that besides the source and gate resistances, most of the parameters such as the channel resistance, drain inductance and intrinsic capacitance are found to be significantly different to those in the saturation mode of operation. The subthreshold channel resistance increases and the drain inductance decreases as the finger number increases because of the more significant charge transport along the finger boundaries. In addition, the channel resistance can be governed by the drain-induced barrier lowering in a transistor with very short gate length. The equivalent intrinsic capacitance of the small-signal equivalent circuit is governed by the substrate resistance and capacitance which make the parameter extraction more difficult.     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

The influence of substrate bias upon the AC characteristics of MOS transistors

In applications where MOS transistors are used in the "variable-resistor" region, it is often useful to bias the bulk with respect to the source in order to control the dc value of the channel resistance. What this biasing of the substrate means for the small signal coefficients--the mutual conductance and the amplification factor--is calculated, and agreement between calculated and measured values is shown.     

New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.