Error Analysis of the Kmetz/Maenner Algorithm

Use of low-precision logarithms can minimize power consumption and increase the speed of multiply-intensive signal-processing systems, such as FIR filters. Although straight table lookup is the most obvious way to compute the logarithm, Maenner claims to have discovered a technique that produces four extra bits at no cost. We analyze Maenner's technique and show that in fact the technique provides only one extra bit of precision. A related technique by Kmetz, which has never been analyzed before, is shown here to be more accurate than Maenner's. We compare these techniques to the more complex bipartite technique, and show that Kmetz's technique takes less memory for systems requiring fewer than ten bits of precision.     

Parameterized High Throughput Function Evaluation for FPGAs

This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters, multipliers, and dividers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, (4) shift-and-add based CORDIC units, and (5) rational approximation. Our treatment mainly focuses on explaining method (3), and briefly covers the background of the other methods. For lookup-multiply units, we provide equations for estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. A selection of the compared methods are implemented as part of the current PAM-Blox module generation environment. An example shows that the lookup-multiply unit produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units. Additionally, the lookup-multiply method or rational approximation can produce efficient designs for larger data widths when evaluating functions not supported by CORDIC.     

浮点倒数查找表的构造

在浮点除法器的设计中，若用函数迭代或高基数算法进行除法运算，计算开始时，通过浮点倒数查找表获得一个较精确的初始除数倒数近似值，可以减少除法的迭代次数，缩短运算的延迟。即将除数的前几位作为表的一个入口地址，该地址指示的位置存放着满足一定精度的初值倒数近似值。文中详述了几种获得除数倒数近似值的方法，其中包括算法、误差限和精度等。     

A Decimal Floating-Point Divider Using Newton–Raphson Iteration

Increasing chip densities and transistor counts provide more room for designers to add functionality for important application domains into future microprocessors. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE P754). In this paper, we presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. The design uses an efficient piecewise linear approximation, a modified Newton–Raphson iteration, a specialized rounding technique, and a simplified decimal incrementer and decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the decimal divider, which is compliant with the current version of IEEE P754, has an estimated critical path delay of 0.69 ns (around 13 FO4 inverter delays) when implemented using LSI Logic’s 0.11 micron Gflx-P standard cell library.

微处理器的快速开方计算方法

在基于微处理器的自动控制系统中对有效值进行等量计算时,针对利用传统开方算法计算存在速度慢、效率低,对实时控制算法和结果产生不利影响的缺点,提出了一种基于迭代思想的新型开方算法。该算法在使用时先确定计算初值,然后只需进行简单的整数除法等运算即可快速完成开方计算,计算结果具有较高的精度,大幅减少计算周期,提高了计算效率。且该算法不受微处理器内部资源限制,适用于普通8位、16位单片机和DSP等,支持整数开方和浮点开方计算。     

一种基于查找表的移位寄存器链的设计

提出了一种基于查找表的移位寄存器链的设计,以查找表的配置存储单元作为移位模块,以查找表的输入信号作为移位地址选择信号,通过对时钟和写使能的控制进行移位操作.1个查找表最大实现32个时钟周期的移位操作,4个查找表通过配置,可实现4条相互独立的32位移位寄存器链,或首尾级联实现一个128位的移位寄存器链.基于28nm工艺,...     

具有非线性突触的BP神经网络模型及其性能分析

本文提出了一种新的ＢＰ网络模型及其相应的算法。这种模型采用具有非线性特性的自适应查表单元来模拟神经元的突触，从而为网络的学习提供了全局最优的收敛特性以及省时的迭代和快速收敛等优点。     

The Negative Two’s Complement Number System

The two’s complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from −1 to one least significant bit below +1. Either the multiplication of −1 • −1 or taking the absolute value of −1 produces a result (+1) that cannot be represented. A new system, the negative two’s complement number system, is described here that has a range of one least significant bit above −1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

基于流量分布的高速路由表查找算法

IP路由表查找是实现高性能路由器的主要瓶颈。根据IP业务流量分布特性，在现有的路由表查找技术的基础上，提出了基于流量分布的高速路由表查找算法。     

基于DCT变换的快速分形编码方法

本文提出了一种基于DCT变换加速相似块匹配的分形编码方法.通过图像块与相似块在DCT变换域少数低频系数的比较,来确定匹配的相似块.并根据DCT变换的性质,方便的确定对比度因子和亮度偏移量.并采用将图像块与相似块的DCT变换系数预制成查找表的方法减少重复运算.结果表明,编码时间大幅度减少,而PSNR只是略有下降.     

基于脉动阵列的复数定点QR分解VLSI设计

提出一种应用Givens变换实现QR分解的脉动阵列中的边界单元和内部单元电路结构。在硬件成本增加不多的条件下,应用牛顿-拉夫逊迭代方法和查询表技术,实现了平方根倒数的快速计算。综合的电路工作时钟达100MHz,两种单元的数据处理周期均为120ns,阵列数据处理速度高于相关文献报道40%以上。     

根升余弦脉冲成形滤波器FPGA实现

提出了基于电路分割技术实现通信系统发送端根升余弦波形成形滤波器查表法的FPGA结构,节省了ROM单元,讨论了其ROM初始化时形渡数据的组织方法,完成了该结构的VHDI。实现,给出了该设计在Modelsim环境下的时序仿真结果。通过对仿真结果分析,表明所述的设计方法是可行的。该设计方案不随波形样本数目的增多而使电路系统变得更为复杂,它所实现的成形滤波器满足于高速成形的应用需求。     

雷达杂波视频信号实时仿真与系统实现

阐述了在雷达多目标仿真系统中杂波相干视频信号模型的建立过程和实时仿真系统的设计及实现。针对仿真过程中非正态随机序列的产生,提出用随机向量法和查表法进行零记忆非线性变换。随机向量法完成线性变换,查表法完成非线性变换,以产生具有指定概率分布和功率谱的非正态相干随机序列,复现与雷达信号具有相参性的杂波相干视频信号。仿真结果证明这些方法的正确性和实用性。     

图像传感器MT9M034输出图像数据的校正

针对高动态范围图像传感器MT9M034输出图像时进行实时数据压缩引入的误差,分析研究了该误差对基于CLAHE色调映射算法的影响,并给出了误差校正方法和FPGA实现电路。实验结果显示,误差校正方法减小了该误差影响,且改善了CLAHE色调映射处理的效果。     

Implementation of the Exponential Function in a Floating-Point Unit

In this work we present an implementation of the exponential function in double precision, in a unit that supports IEEE floating-point arithmetic. As existing proposals, the implementation is based on the use of a floating-point multiplier and additional hardware. We decompose the computation into three subexponentials. The first and third subexponentials are computed in a conventional way (table look-up and polynomial approximation). The second subexponential is computed based on a transformation of the slow radix-2 digit-recurrence algorithm into a fast computation by using the multiplier and additional hardware. We present a design process that permits the selection of the most convenient trade-off between hardware complexity and latency. We discuss the algorithm, the implementation, and perform a rough comparison with three proposed designs. Our estimations indicate that the implementation proposed in this work presents better trade-off between hardware complexity and latency than the compared designs.     

4G系统中数字AGC技术研究与FPGA实现

在4G无线通信系统中,需要自动增益控制 (Automatic Gain Control,AGC) 模块来扩大接收机的动态范围,同时保证系统响应时间。提出了一种基于4G下行同步码平均功率检测的数字AGC算法,在同步信号的控制下,此算法运用滑动窗方法在一定时间内来提取相关运算平均功率的最大值,然后在查找表内查找出此时的控制字,最后经过运算后送入数控衰减器。此算法运用MATLAB进行仿真验证,然后在FPGA内进行了设计与实现。测试结果表明,该算法功能正确,且系统响应时间快速。     

Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices

Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.

一种低复杂度的并发双频数字预失真模型

由于多标准通信制式的发展,并发双频功率放大器的数字预失真线性化技术近年来备受关注。文中提出一种低复杂度的并发双频数字预失真模型。与已报道的简化二维记忆多项式模型相比,该模型通过引入同阶包络交叉项增强对双频功率放大器中非线性互调失真的补偿能力。新模型能够取得比简化二维记忆多项式模型更好的建模精度和线性化性能,同时保持了便于利用一维查找表实现的优点。对新模型与其它双频模型的线性化性能与模型复杂度进行了比较,仿真与测试结果表明新模型在性能和复杂度之间取得了良好的折中。     

基于VHDL语言的快速查表电路

介绍了用超高速集成电路硬件描述语言(VHDL),设计数字集成系统中快速查表电路的方案,这种查表算法具有并行运行的特点,并能够同时查找多种参数.该查表电路用FPGA予以实现.