硬盘驱动器磁头静电放电的灵敏度测试

提高硬盘密度的竞赛导致盘读头中传感器更小,灵敏度更高。近年来,读头中感应式传感器已为磁阻式传感器(MR)所取代。MR传感器阻抗随盘面磁场而改变,硬盘驱动器将盘面磁场转换为数字数据。现在,MR传感器,或者说磁头,给极高灵敏度磁阻式巨传感器(GMR)开辟了道路。(本文的词汇“传感器MR”以及“磁头”是相通的。) GMR磁头,即薄膜半导体,恰好可认为是最好的静电放电(ESD)检测器。因此,GMR磁头制造厂对他们产品的ESD敏感性进行检验,采用更牢靠的设计,以期在市场中获利。能经受更大的放电而不损坏或者传输曲线变化较少的磁头将对硬盘驱动器制造厂更具有吸引力。 GMR磁头对静电敏感也使得硬盘驱动器制造厂甚为头疼。驱动器制造厂利用这些测试结果决定哪种GMR磁头可在新的驱动器设计中采用。测试也指明驱动制造厂需在他们的装配区域使用何种程序的ESD     

分析电子通信产品的ESD防护设计

电子产品在设计、实验、生产、运行、维修过程中通常会有静电释放(ESD),而静电释放是一个隐性杀手,它会干扰产品的正常工作,损坏电子元器件,积累过多会引起火灾、爆炸等事故。因此,必须加强对电子通信产品ESD的防护。本文简单阐述了ESD在电子通信产品中的危害及现有ESD防护设计中存在的不足,提出了ESD设计的改进优化措施。     

机械手在磁头动态性能自动化测试系统中的应用

硬盘磁头动态测试是磁头生产过程中反映硬盘性能最为直接有效的测量手段,也是硬盘生产厂家投入较大的工序.为了保证产品质量,提高工作效率,降低成本,提升企业的竞争力,必须开发出一套适合无尘生产环境要求的磁头自动化测试系统.针对公司硬盘磁头动态测试的特殊性,以EPSON工业机器人为执行机构,采用CCD摄像机建立了机器人手眼视觉系统,开发出基于机械手的磁头动态性能自动化测试系统,提高了测试系统的性能,减少了对操作人员的需求.     

电子通信产品ESD防护设计研究

电子通信产品在设计、试验、生产、运行等的过程中,通常会有静电放电(ESD),而使产品的工作受到干扰,损坏产品的电子元器件,从而引发比较严重的故障,其带来的损失是比较大的。因而,人们对于电子通信产品ESD的防护设计更加重视。本文主要对ESD带来的危害及目前关于ESD防护方案存在的不足进行了分析,并进一步介绍了电子通信产品ESD防护设计所要注意的问题,及防护方法。     

ESD的防护策略

通过对现行的一些ESD防护方案的分析,发现了它们的缺陷：对电气应力与静电放电区分不清,系统未能有效地识别：提出了确立防护方案的基本条件：明确系统的防护等级,遵从各类标准的性能指标要求,实施ESD管理.并结合生产的实际情况,从防护等级的确立、数据的获取、装置的监控、防护措施的确定以及防护方案的实施,讨论了工业生产中的ESD防护;从包装材料的筛选、包装的检查、包装标注和测试,分析了ESD防护包装的具体实现;从工作面、工作间的测试和接地的有效搭接,研究了ESD的防护与控制策略.     

分析电子通信产品的ESD防护设计

对于电子通信产品而言,静电释放(ESD)是一个隐性杀手。在电子通信产品的生产使用过程中,对电子通信产品静电放电,不但会使产品的正常工作遭到干扰,同时还可能造成电子通信产品电子元器件的损坏,使电子通信产品出现故障,严重者还可能引起事故的发生。因此,加强对电子通信产品的ESD防护设计至关重要。本文在阐述了电子通信产品静电释放的危害及其ESD防护设计要求的基础上,进一步分析了电子通信产品的ESD防护设计的方法。     

静电对点阵类LCD造成显示性能影响初探

通过对静电产生机理、静电放电模型、ESD的防护与测量等进行分析，结合LCD生产过程中静电对产品的损坏实例进行机理分析，并采取措施以减小静电对产品的影响，为LCD、LCM生产过程中静电防护提供参考。     

ESD对微波组件的危害及其防护

在微波组件的生产过程中,静电放电(ESD)是导致产品失效的主要原因之一。介绍了ESD损伤的失效类型,分析了ESD对微波组件造成的危害特点,阐述了在微波组件设计和生产中静电防护的重要性,以及所采取的ESD防护管理方法和ESD防护的具体技术措施。     

基于电子通信产品的ESD防护设计方法研究

电子通信产品ESD防护设计情况直接关系着设备的质量与使用情况,会不同程度的影响着设备经销商对产品的推广,对于企业的经济与社会效益都有着重要影响,这些问题都对产品在市场竞争中的地位及未来的生存与发展起到重要作用。所以,在进行电子产品设计与生产过程中,ESD防护设计是不可忽视的重要环节。因此,本研究主要介绍了ESD对电子通讯产品的危害,电子通信产品ESD防护设计中的缺陷,电子通信产品静电防护设计的要求及注意事项,并探讨了电子通讯产品ESD防护设计的方法。     

纳米集成电路的静电放电防护

综述了纳米集成电路片上(On-Chip)静电放电防护(ESD)的研究现状;结合自身流片数据,阐述其ESD防护机理和设计要点。从器件ESD防护机理入手,逐步深入分析阐述了纳米集成电路的新特征、纳米器件的失效机制以及基于体硅CMOS工艺和SOI工艺的基本ESD防护器件。在此基础上,对纳米集成电路ESD主要热击穿失效的热量产生机制、热耗散问题,以及边界热电阻对ESD防护带来的影响进行了分析,提出了利用纵向散热路径和工艺整合方案来提高纳米集成电路中ESD防护器件鲁棒性的有效措施。     

ESD phenomena in GMR heads in the manufacturing process of HDD and GMR heads

It is well known that giant magnetoresistive (GMR) heads used for hard disk drives (HDD) are very sensitive to electrostatic discharge (ESD). In this paper, we describe a method of categorizing ESD damage modes from a standpoint of magnetic influences on the heads as observed by quasi-static test (QST) characteristics as well as electromagnetic characteristics like off-track profiles. In addition, we report an example of GMR stack interlayer diffusion which is one type of hard ESD damage. We also present an example of ESD damage that happened in an actual production process and its preventive measures as guidelines.     

ESD SPICE model and measurements for a hard disk drive

A simple lumped RLC model for a hard disk drive is developed and used in SPICE circuit simulations. Simulation results were compared with experimental measurements using a special “hybrid” disk drive to validate the SPICE model. The voltage on and between the head and disk inside the drive were modeled during an ESD event to the baseplate and/or disk. Experimental measurements and SPICE modeling show that if the disk grounded when there is a large disk-to-base resistance, then head-to-disk electrical breakdown can occur. It is concluded that an electrical model is valuable in developing an understanding of the effects of ESD on a hard disk drive.     

RFID的多功能ESD保护电路设计

设计了一个适用于RFID的多功能ESD保护电路，并对其工作原理和测试结果进行了论述。这个保护电路不仅能够进行传统的ESD保护。还可以避免内部电路因受到过大场强而产生的高电压造成的损坏，实现RFID限压功能．将狭义的ESD保护电路推广为广义的限压保护电路。仿真结果表明，此电路性能完全符合ISO／IEC 10373国际标准的要求。这种新的设计方法大大缩小了芯片版图面积，进而降低了芯片成本。     

全过程控制的ESD防护管理

介绍了ESD（静电放电）现象,阐述了静电敏感器件（SSD）在电子产品研制、生产全过程中必须采取的静电防护措施,以及通过实时监控系统来实现静电防护的闭环管理。     

减薄划片过程中ESD的预防与控制

SED在IC封装过程中对IC产品质量的影响越来越大。以生产过程中遇到的一些实际问题为例,分析探讨了ESD在封装生产过程对产品造成的影响,成因以及ESD的预防与控制方法。     

Field failure mechanism and improvement of EOS failure of integrated IGBT inverter modules

In this paper, we have proved that the soft damage from human body ESD can actually cause EOS damage, while integrated IGBT inverter modules (or intelligent power modules) are operating. Failure mechanism was defined as a latchup phenomenon by ESD damage leakage. Failure modes of each failed IGBT inside two integrated IGBT inverter modules were soft and hard burnout, respectively. To determine the failure mechanism, we have done fault tree analysis. From this analysis, we could conclude the main factor as the ESD event between device ESD immunity and PCB assembly line. In addition, from the PCB assembly line, we have identified damage samples due to an ESD event. Based on this result, we have implied ESD on IGBT and intentionally caused a leakage, then applied the device to the system. After an aging test, we could reproduce soft burnout and hard burnout.     

Possible new mechanism of chip latent damage due to ESD

This paper introduces a possible new, to-date not recognized mechanism of microelectronic chip damage due to ESD as well as numerical simulation of some corresponding damage scenarios for an ESD protection device.The model presented herein recognizes the effects of thermo-mechanical coupling that can produce excessive mechanical stresses, elastic shock waves and mechanical damage in a chip during an ESD event. This mechanism can get activated at temperatures well below melting point and thus may be an early contributor to latent and “hard” ESD failures.     

Characterization of defects in flexible circuits with ultrasonic atomic force microscopy

Flexible circuit technology is a key factor in the continued shrinkage of microelectronic components and devices. One of the important applications of the flexible circuits is in hard disk drive industry, where they are used as an interconnection between the preamplifier and head slider assembly of a hard disk drive. At present, defect characterization of flexible circuits is often performed after manufacture usually with optical microscopy. While this may be sufficient for certain low-tech applications, for advanced ultra high-density hard disk components may not be enough. With a continuing reduction of the dimension of the current carrying conductor wires, the size of defects that may affect long-term reliability of the system is reaching the resolution limit of traditional techniques used to characterize the defects. This paper presents combined application of atomic force microscope (AFM) and ultrasonic atomic force microscope (UAFM) to characterize defects in flexible circuits. Three identical flexible circuits from different manufactures are examined using AFM and UAFM. The AFM and UAFM images of a particular region, in the flexible circuit in all the three samples are compared. Images from pure polymer region of the flexible circuit are compared with the images of the regions containing copper and polymer. In general, the UAFM images show subsurface features while AFM images show surface topography. This capability of UAFM can be used to image the grain structure of the copper film without removing the polymer cover layer film. It also detects the sub-micron defects present at the polymer/metal interface. Analysis of the grain structure of copper, distribution of defects at the polymer/metal interface is presented. Based on these observations, the applicability of AFM/UAFM to image the microstructure of copper in flexible circuits and possible effect of defects in flexible circuits on the long-term reliability of the hard disc drive are discussed.     

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.     

E2PROM工艺的ESD保护电路失效分析

ESD保护电路已经成为集成电路不可或缺的组成部分,如何避免由ESD应力导致的保护电路的击穿已经成为CMOSIC设计过程中一个棘手的问题。光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、微红外发光显示设备EMMI等的应用可以揭示ESD保护电路的失效原因及机理。文章通过对一组击穿失效的E2PROM工艺的ESD保护电路实际案例的分析和研究,介绍了几种分析工具,并且在ESD失效机制的基础上,提出了改进ESD保护电路的设计途径。