低压低功耗模拟集成电路设计技术及展望

随着集成电路设计技术及其应用发展,我国在低压、低功耗模拟集成电路的设计和应用方面取得了较好的成绩。但是,由于多种因素的限制,现阶段我国低压低功耗模拟集成电路设计与国际先进水平相比仍存在较大差距。基于此,本文对低压低功率模拟集成电路设计特点展开分析,并对低压低功耗模拟集成电路设计的未来发展进行简要描述,以期可以更好地应用于我国各行各业中。目前,我国CMOS工艺水平不断提高,随着芯片应用频率的逐渐提高,低压低功耗集成电路设计的选择成为当前关注的焦点,尤其是CMOS技术的应用效果更为重要。     

硅模拟集成电路

本文综述了国内外模拟集成电路的发展动态，叙述了国内模拟集成电路与国外的主要差距，针对国内的具体情况，提出了发展我国模拟集成电路的观点对策。     

数字化时代的模拟集成电路

文章介绍了数字化时代对模拟集成电路提出的挑战。从模拟集成电路的广阔发展空间、稳步的市场增长、不断出现的产品性能新水平、技术发展新趋势、以及极大的市场潜力和大好的发展机遇等方面，说明模拟集成电路在数字化时代存在的意义以及模拟集成电路的发展前景。     

模拟集成电路发展研究

综述了国外模拟集成电路市场概况、器件的发展趋势及工艺发展现状；对如何发展我国的模拟集成电路提出了建议。     

国外模拟集成电路发展动态

综述了近年来国外模拟集成电路的发展趋势,介绍了国外模拟集成电路的市场情况以及模拟IC器件和工艺技术的发展动态,在产品动态方面,着重介绍了运放 A/D、D/A转换器的情况.     

双极模拟集成电路抗辐射加固技术跟踪

介绍了国外硅双极模拟集成电路抗辐射加固技术的发展动态和γ射线、中子、高能重离子对双极模拟集成电路的辐射效应及其电路结构器件结构、工艺控制等关键加固技术。以极模拟集成电路的辐射损伤阈值。     

模拟集成电路原理与应用（上）

一、模拟集成电路概述电子电路中的工作信号,不外乎有数字信号和模拟信号两种类型。所谓模拟信号,是指那些在时间上和数值上都是连续的信号。我们将工作于模拟信号下的电子电路,统称为模拟电子电路(简称模拟电路)。多年来,模拟电路从分立元件的电子管、晶体管发展到单片集成电路。模拟集成电路又从双极型发展到晶体管和场效应管混合型或晶体管和MOS场效应管混     

模拟集成电路发展概况

模拟集成电路(IC)是现实世界和数字化系统之间的桥梁，是现代信息化系统的关键技术之一。从总市场、分类市场、设计和工艺技术、产品水平以及技术发展趋势等方面，介绍了模拟集成电路的发展状况，并提出了发展中国模拟集成电路技术的基本观点。     

模拟集成电路市场走向

模拟集成电路的品种繁多,制作工艺复杂,生产也常常难以形成规模,因而人们普遍关心的问题是:从事模拟集成电路生产是否有利可图?研究世界模拟集成电路市场发展动态与趋势,或许会给你几分惊喜、几分启发。     

行为级硬件描述语言XHDL的模拟机制

本文介绍了一种集成电路行为级硬件描述语言ＸＨＤＬ，以及利用ＸＨＤＬ如何进行电路的高层次描述，在此基础上着重讨论了ＸＨＤＬ的模拟机制。     

模拟集成电路设计工具的研究进展

介绍了模拟集成电路设计自动化工具的研究进展 ,详细叙述了有关模拟 IC设计自动化(DA)所用到的种种方法以及各种方法的优劣 ,提出了一些解决方案。介绍了模拟硬件描述语言(AHDLs)以及目前开发混合信号和混合层次 EDA的情况 ,最后叙述了所开发的基于知识的自动化器件产生器。器件产生器的设计思想有效地使用了电路模拟器和从它所得到的信息 ,且器件产生器自适应于工艺过程 ,因此既有基于模型设计系统的短设计时间 ,又有基于模拟设计系统的精确性 ,而且它提高了第一次投片成功率与设计周期之比。     

切比雪夫Ⅱ型模拟高通滤波器的设计及实现

提出了一种基于反相积分器的信号流图来实现切比雪夫Ⅱ型模拟高通滤波器的方法。首先,基于归一化切比雪夫Ⅱ型模拟低通滤波器极点分布的特点,推导出归一化切比雪夫Ⅱ型模拟低通滤波器零极点和转移函数的公式,得到归一化切比雪夫Ⅱ型模拟低通滤波器设计的步骤;然后,基于频率变换与逆变换,提出一种利用归一化切比雪夫Ⅱ型模拟低通滤波器来设计切比雪夫Ⅱ型模拟高通滤波器的方法;最后,给出了利用归一化切比雪夫Ⅱ型模拟低通滤波器来设计切比雪夫Ⅱ型模拟高通滤波器的实例及其实现电路。     

State of the art in the analog CMOS circuit design

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.     

多用户毫米波MIMO系统中基于信道互易性的混合模数预编码算法

本文针对多用户毫米波多输入多输出(Multiple Input Multiple Output,MIMO)系统,首次提出了分离子阵列MIMO混合模数预编码架构毫米波系统的一种模拟接收方案。将最大化和速率求解混合模数预编码的三元联合优化问题分成模拟和数字两部分求解,进一步提出了基于信道互易性的混合模数预编码算法。该算法通过最大化下行各个用户和上行各个子阵列的接收信干噪比分别求解模拟合并矢量和模拟预编码矢量;优化模拟部分后,设计发射端数字预编码器消除多用户数据流之间的干扰。数值仿真表明所提算法收敛速度快,且可获得接近最优纯数字预编码算法的性能。      

Demonstration of an Analog IC Function Maintenance Strategy, Including Direct Calibration, Built-in Self-test, and Commutation of Redundant Functional Blocks

A new analog subsystem maintenance strategy is presented that can be used to improve the accuracy, reliability, yield, and testability of analog and mixed-signal ICs. This scheme is a generally applicable design approach that combines hybrid redundancy, direct subcircuit parameter adjustment (calibration), and on-chip analog function verification (built-in self-test). Improvements are realized in a system-transparent fashion through careful function block commutation. The cost is a moderate die area increase. This design strategy is applicable to a wide range of moderately complex analog functions. An example analog function is used here to illustrate this new maintenance approach. Experimental data demonstrate the capabilities of this new approach to analog IC design fortestability.     

Analog/digital ASIC design for testability

The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing. These are examined for commonly used analog functions, and the results culminate in an architecture for testable mixed analog and digital circuits. The architecture is designed to solve the problems associated with testing basic circuit configurations for different types of commonly used analog macros. Using the recommended architecture to gain access to control and observation test points in the analog portions of the mixed analog/digital ASIC, a series of analog test tables for several different analog functions have been derived. The analog test procedures are independent of any digital design for testability that might be used in the digital portions of the ASIC. General testing procedures for current analog/digital ASICs are described along with desirable characteristics for testers for this type of circuit     

Convergence Speed and Throughput of Analog Decoders

This letter is concerned with the implementation of iterative decoding algorithms in analog integrated circuits. We study the convergence speed and the throughput of analog decoders for low-density parity-check codes, and show that they depend on the code, the decoding algorithm, the signal-to-noise ratio, and the average time constant of the analog circuit interconnections. However, they are not a function of the variance of the time constants. The analysis presented here can be used for selecting suitable codes and decoding algorithms for analog decoding. Furthermore, it can be used to estimate the throughput of an analog decoder, if the average time constant of the analog circuit is known     

GaAs HBT's for analog circuits

Silicon bipolar integrated circuit (IC) technology has dominated the analog IC world for over two decades. As the push for wider bandwidths with higher precision continues, the emergence of GaAs HBT technology is destined to challenge silicon bipolar's domination at the high end of the analog market. This paper discusses the analog application areas best suited to GaAs HBT technology, points out its unique characteristics for analog circuits, describes the design issues for key analog building block circuits, and provides comparative examples of demonstrated state-of-the-art analog circuits. Finally, a projection of future direction in this application area is provided     

现阶段模拟移动网发展方向探讨

随着数字移动通信的迅猛发展,第一代模拟移动通信已呈日趋萎缩的迹象。本文作者以泉州市的一些具体数据对模拟网的萎缩进行限说明,并着重指出,在现阶段应通过下调模拟网资费、作为市话网的延伸和补充,开展移动公用电话和租机业务以及缩减模拟网规模等手段,挖掘模拟网的潜力,使之发挥最大的经济效益。     

一种基于GMD分解的混合预编码算法

提出了毫米波大规模MIMO系统中一种利用几何均值分解(GMD)设计模拟和数字预编码矩阵的算法.首先根据初始模拟预编码矩阵列向量相互正交,利用GMD分解计算出模拟预编码矩阵后,取其元素相位构成的矩阵为最终的模拟预编码矩阵,然后设计数字预编码矩阵.仿真结果表明,频谱效率和误码率较正交匹配追踪(OMP)算法分别有大约3dB和2.5dB的增益.