半导体激光器的低频电噪声谱密度和器件的可靠性

本文给出了半导体激光器的低频电噪声谱密度和器件可靠性关系的实验结果。     

Low-frequency noise of thick-film resistors as quality and reliability indicator

The non-linearity and the noise of thick-film resistors are parameters that can be used to make a prediction of resistor reliability. The noise spectroscopy measurements of thick-film resistors are proposed as a diagnostic tool for the prediction of possible types of failure. The correlation between noise spectral density data and the results of accelerated aging of thick-film resistors at high temperature were made for HS80 and 2000 resistor pastes.     

Validation and test issues related to noise induced by parasitic inductances of VLSI interconnects

Shows the results of studies of noise induced by various combinations of parasitic capacitances and inductances. Interconnects are simulated with parameters obtained from a 0.18 /spl mu/m process. The four kinds of noise addressed are (i) crosstalk pulse; (ii) crosstalk speedup and slowdown; (iii) oscillatory noise; (iv) combination of oscillatory noise and crosstalk pulse. The crosstalk effects induced by a combination of mutual capacitance and mutual inductance can be larger than those induced by mutual capacitance alone, even if capacitive crosstalk dominates. For certain interconnects that are capacitively and inductively coupled, transitions in the same direction on an aggressor and victim line can cause speedup or slowdown, depending on timing parameters. A similar observation holds for transitions in opposite directions. We also observe that oscillatory noise can combine with crosstalk pulse under certain skew conditions and give rise to a large magnitude of noise. We show that inductance induced noise can be a problem in medium length interconnects. Because such interconnects can occur in combinational logic blocks, the generation of suitable vectors for test and validation of such logic blocks is of concern.     

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

Optimization of throughput performance for low-power VLSI interconnects

The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance.     

Low-frequency noise and phase noise in MESFETS with LTG-GaAs passivation

We report measurements of the low-frequency noise and phase noise of conventional unpassivated GaAs metal semiconductor field-effect transistors (MESFETs) and of MESFETs fabricated using an overlapping-gate structure and the low-temperature grown (LTG) GaAs as a passivation layer. The noise of the LTG-GaAs passivated MESFET was found to behave quite differently from that of a conventional MESFET and to be significantly reduced at low offset frequencies. These observations are explained in terms of the surface passivating effect of the LTG-GaAs. Low-frequency noise measurements seem to support the idea that the LTG-GaAs passivation reduces the number of active traps, in particular traps with large activation emergies. These results indicate that LTG-GaAs passivation can substantially reduce the near-carrier phase noise of MESFET-based oscillators.     

Low-frequency noise in heterojunction FETs with low-temperaturebuffer

Low-frequency noise was measured on heterojunction FETs grown on low-temperature buffer and superlattice buffer layers. A distinct generation-recombination noise source with an activation energy of 0.70 eV was observed in devices built on a low-temperature buffer. Both structures showed a trap with an activation energy (~0.50 eV) that has a gate-to-source voltage dependence and is believed to be due to interactions between electrons in the channel and traps in the AlGaAs supply layer. Computer simulations of the position of the energy levels as a function of the gate voltage support this idea. A trap due to DX centers with an activation energy of ~0.30 eV in AlGaAs was also observed in both devices     

Microstructure and reliability of copper interconnects

The effects of texture and grain structure on the electromigration lifetime of Cu interconnects are reported. Using different seed layers, (111)- and (200)-textured CVD Cu films with similar grain size distributions are obtained. The electromigration lifetime of (111) CVD Cu is about four times longer than that of (200) CVD Cu. For Damascene CVD Cu interconnects, the electromigration lifetime degrades for linewidths in the deep submicron range because the grains are confined as a result of conformal deposition in narrow trenches. In contrast, electroplated Cu has relatively larger grains in Damascene structure, resulting in longer electromigration lifetime than CVD Cu and no degradation for linewidths in the deep submicron range     

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.     

Low-frequency noise in gallium nitride epitaxial layers with different degrees of order of mosaic structure

The correlation between the noise level 1/f and the degree of mosaic-structure order in gallium nitride epitaxial layers was studied for the first time. Samples with a doping level of N _d ?N _a ≈8×10¹⁶ cm^?3 and a relatively high degree of order were characterized by the Hooge parameter α≈1.5×10^?3. This value is unprecedently low for thin GaN epitaxial films. The Hooge parameter was significantly higher for samples with N _d ?N _a ≈1.1×10¹⁸ cm^?3 and a low degree of order despite the fact that α generally decreases with increasing doping level at the same degree of order. Thus, the degree of mosaic-structure order affects not only the optical and electrical characteristics but also the fluctuation parameters of GaN epitaxial layers.     

An improved RC model for VLSI interconnects with applications to buffer insertion

A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from HSPICE as a bench mark, we show that among all 18 models studied, the π-configuration of AWE-RLC model yields the best accuracy. To reduce complexity subsequently computational cost without sacrificing accuracy, the AWE-RLC model is mapped to a complex RC model using moment matching. The complex RC model is further mapped to an improved RC model utilizing the principle of charge reservation. The improved RC model is employed to estimate the delay of long interconnects with buffer insertion. As compared with the conventional RC model, the improved RC model reduces the delay of interconnects with buffer insertion, the number of buffers, and the size of the buffer by 20.5, 24, and 32 %, respectively.     

Low-frequency noise in SOI pseudo-MOSFET with pressure probes

Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (Ψ-MOSFET) configuration. 1/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed.     

Low-frequency intensity noise in c.w. (GaAl)As d.h. lasers with stripe geometry

The excessively large low-frequency intensity noise above threshold observed in some C.W.-operated (GaAl)As d.h. lasers with stripe geometry is shown to result from spatially inhomogeneous gain saturation. Improved understanding of the noise properties yields new information concerning the formation mechanism of the nonlinear output/current curves.     

Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate

We report the low-frequency noise characteristics of ultrathin body (UTB) p-channel MOSFETs with molybdenum (Mo) as the gate material. Using the number fluctuation model with correlated mobility fluctuation, the dependence of the noise behavior on bias condition is explained. The impact of nitrogen implantation (for gate work function engineering) on the noise behavior is also presented. An exponential increase in noise with nitrogen implant dose is attributed to interface-trap generation caused by nitrogen penetration through the gate oxide.     

Full-wave modelling and broadband characterization of coupled interconnects in high-speed VLSI

A time-domain full-wave method for the extraction of broadband equivalent circuit parameters of symmetrical coupled interconnection lines on chips is presented. This method is based on the two-dimensional finite-difference time-domain method. After determination of the even and odd mode propagation constant γ and characteristic impedance Z _c of the lines, the RLGC matrices per unit length can be obtained. Many techniques are proposed and used during the time-domain analysis to improve the efficiency. The circuit parameters extracted can be inserted into circuit simulation software to investigate the time-domain responses of high-speed integrated circuits on chips. The reliability of this method is verified by its applications to typical problems.     

Low-frequency noise characteristics of Gallium Arsenide MESFETs

Gallium Arsenide is a complex material with a high defect density and a poor surface. It is possible that several low-frequency noise producing mechanisms may occur in a single device. This note shows one such case.     

Low-frequency noise spectroscopy of polycrystalline siliconthin-film transistors

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap     

Low-frequency noise of ion-implanted double-drift IMPATT diodes

The low-frequency open circuit noise spectral density S(f) of an ion-implanted 60-GHz double-drift-region IMPATT diode was measured as a function of the dc avalanche current I0. Over an intermediate current range the noise follows an S(f)=a²VB0²/I0relationship where VB0is the reverse breakdown voltage and a²≃4.5 × 10^-20A/Hz.