深亚微米三栅FinFET短沟道效应和拐角效应计算机模拟分析

利用三维器件模拟软件,研究了深亚微米三栅FinFET的短沟道效应,并模拟了阈值电压和亚阈值摆幅随硅鳍(fin)厚度和高度的变化情况.通过优化硅鳍厚度或高度,可以有效的控制短沟道效应.在进一步对深亚微米三栅FinFET的拐角效应进行二维数值模拟的过程中,并未观察到由拐角效应引起的泄漏电流.与传统的体硅CMOS结构有所不同,拐角效应并未使得深亚微米三栅FinFET性能变差,反而提高了其电学性能.     

沟道长度及源/漏区掺杂浓度对MOS-CNTFET输运特性的影响

碳纳米管场效应晶体管电子输运性质是其结构参量(纵向结构参量:如CNT的直径、栅介质层厚度、介质介电常数等;横向结构参量:如沟道长度、源/漏区掺杂浓度等)的复杂函数.本论文在量子力学非平衡格林函数理论框架内,通过自洽求解泊松方程和薛定谔方程以得到MOS-CNTFET电子输运特性.在此基础上系统地研究了沟道长度及源/漏区掺杂浓度对MOS-CNTFET器件的漏极导通电流、关态泄漏电流、开关态电流比、阈值电压、亚阈值摆幅及双极性传导等输运性质的影响.结果表明:当沟道长度在15 nm以上时,上述各性质受沟道长度的影响均较小,而导通电流、开关态电流比及双极性传导特性与源/漏掺杂浓度的大小有关,开关态电流比与掺杂浓度正相关,导通电流及双极性导电特性与源/漏掺杂浓度负相关.当沟道长度小于15 nm时,随沟道长度减小,漏极导通电流呈增加趋势,但同时导致器件阈值电压及开关电流比减小,关态漏电流及亚阈值摆幅增大且双极性传导现象严重,短沟道效应增强,此时,通过适当降低源/漏掺杂区掺杂浓度,可一定程度地减弱MOS-CNTFET器件短沟道效应.     

纳米器件阈值电压提取方法

阈值电压是MOSFET最重要的电学参数,它在器件模拟和电路设计方面起着举足轻重的作用。本文分析总结了目前比较常用的阈值电压的提取方法,分别利用它们提取了FinFET和JLT不同沟道长度的阈值电压,讨论了这些方法在提取两种现代MOS器件阈值电压时的有效性和局限性。     

双沟道层对氮掺杂非晶氧化铟锌薄膜晶体管的影响

采用射频磁控溅射法, 在热氧化p型硅基片上制备了双沟道层非晶氧化铟锌(a-IZO)和氮掺杂氧化铟锌(a-IZON)薄膜晶体管(TFTs), 并研究了双沟道层对器件电学性能和温度稳定性的影响。研究发现, a-IZO/IZON双沟道层TFTs具有较高的场效应迁移率, 为23.26 cm²/(V•s), 并且其阈值电压相较于单层a-IZO-TFTs正向偏移。这是由于氮掺杂可以减少沟道层中的氧空位, 抑制载流子浓度, 使器件具有更好的阈值电压。而a-IZO层避免了由于氮掺杂导致的场效应迁移率和开态电流的下降, 提升了器件的电流开关比。从298 K至423 K的器件转移特性曲线中发现, 双沟道层器件相较于单沟道层器件的温度稳定性更佳, 这可归因于a-IZON层的保护作用。氮掺杂可以减少氧在背沟道层表面的吸收/解吸反应, 改善器件的稳定性。     

短沟道SOI BJMOSFET的阈值电压

提出了一种适用于短沟道SOI BJMOSFET阈值电压特性分析的电荷分享物理模型,详细讨论了短沟道SOI BJMOSFET背界面处于积累、反型以及全耗尽三种状态时的阈值电压,并利用Math-ematica软件进行数值模拟得到阚值电压的特性曲线.通过理论分析和计算机模拟,证明短沟道SOI BJMOSFET阈值电压的可控性很强,更适用于现代ULSI低压低功耗的要求.     

短沟道n-MOSFET亚阈值电流模拟计算分析

本文基于亚阈值电流和表面势模型的基础上,采用商用器件模拟软件,建立了短沟道n-MOSFET的结构和物理模型,对器件的亚阈值电流进行了2-D数值模拟。计算了不同沟道掺杂浓度、氧化层厚度以及沟道长度对器件亚阈值电流的影响,并对模拟结果进行了系统的理论分析,数值模拟结果和解析模型能够在亚阈值区很好的吻合。     

总剂量辐射下的NMOS/SOI器件背栅阈值电压漂移模型

SOI(绝缘体上硅)器件在总剂量辐照下的主要性能退化是由于SOI器件的背栅阈值电压漂移引起的背沟道漏电。本文首先采用二维有限元方法,对辐射在SOI器件的埋氧层中的感生氧化物电荷进行模拟,然后分析此氧化物电荷对器件的外部电学特性的影响,建立了器件在最劣偏置下辐射引起的背栅MOSFET的阈值电压漂移模型,提取背栅MOSFET受辐射影响参数,以用于在SOI电路设计中准确的评估辐射对SOI电路的影响。模拟数据和试验数据具有很好的一致性。     

硅锗应变沟道MOSFET器件中阈值电压的解析模型

在分析应变Si/应变Sil-YGeY/驰豫Sil-XGeX pMOSFET的在栅极电压作用下电荷在栅氧化层下面的分布情况的基础上,通过求解泊松方程,得到此器件的隐埋SiGe沟道阈值电压解析模型和表面沟道的阈值电压解析模型,并用典型参数对模型进行了模拟,得到的模拟结果与实验结果能够很好的吻合.     

一种用于制备大厚度MEMS结构层的浓硼掺杂方法(英文)

在MEMS器件中,浓硼掺杂层通常为器件的结构层.但由于受表面固溶度及浓度梯度影响,该掺杂层(硼原子浓度≥5×1019cm-3)厚度越大所需的扩散时间越长.为了能在同等扩散工艺条件下,制备出更厚的浓硼掺杂层以满足器件要求,提出了多步扩散法.即在保证总的累计扩散时间不变的前提下,将传统的扩散过程分为两个相对短的扩散周期.并且这两个周期连续进行,每个周期各包含一次预扩散和再分布.与传统的两步扩散相比,多步扩散法可为硅基底引入更大量的硼杂质,并且具有一定能力使硼杂质留在一定深度范围内.因此该方法可以获得更大的有效节深.实验中采用该方法成功制备出21μm厚的浓硼掺杂层.然而在文献中提到的采用传统两步法在同样条件下得到的厚度则小于15μm.从而验证了该方法可在同等扩散工艺条件下,可以制备出更厚的浓硼掺杂层.     

氮掺杂非晶氧化铟锌薄膜晶体管的器件稳定性改善研究

采用射频磁控溅射方法,在P型硅基片上制备了非晶掺氮氧化铟锌沟道层及其薄膜晶体管(a-IZO∶N-TFTs)器件,探讨了氮气对a-IZO∶N-TFTs性能和电学稳定性的影响。研究发现,当沉积过程中的氮气流量增加时,a-IZO∶N-TFTs的阈值电压(Vth)不断右移,说明氮气掺杂有效抑制了器件的载流子浓度。在对a-IZO∶N-TFTs进行0~5400 s的栅极正偏压应力测试中发现,通入4 m L/min(标准状态)的氮气能使Vth的变化量从3.77下降到0.72 V,表明氮气掺杂提高了a-IZO∶NTFTs的电学稳定性。然而,同时发现过量掺杂氮气也会造成新的氮相关缺陷从而降低器件的稳定性。     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs

We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage$( V_ th)$, and drain-induced barrier-height lowering are numerically calculated for the device with different channel length ($L$) and the thickness of silicon film$( T_ si)$. Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs,$ T_ si$should be simultaneously scaled down with respect to$L$. From a practical fabrication point-of-view, a DG MOSFET with ultrathin$ T_ si$will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that$ L/ T_ si geq 1$may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.     

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.     

On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.     

Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowering, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire FinFETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.     

Sensitivity of Multigate mosfets to Process Variations–-An Assessment Based on Analytical Solutions of 3-D Poisson's Equation

This paper investigates the sensitivity of multigate MOSFETs to process variations using analytical solutions of 3-D Poisson's equation verified with device simulation. FinFET and Tri- gate with both heavily doped and lightly doped channels have been examined regarding their immunity to process-induced variations and dopant number fluctuation. Our study indicates that lightly doped FinFET has the smallest threshold voltage (V_th) dispersion caused by process variations and dopant number fluctuation. For heavily doped devices, dopant number fluctuation may become the dominant factor in the determination of overall V_th variation. The V_th dispersion of Tri-gate may therefore be smaller than that of FinFET because of its better immunity to dopant number fluctuation.     

An Enzyme Switch Employing Direct Electrochemical Communication between Horseradish Peroxidase and a Poly(aniline) Film

An enzyme switch, or microelectrochemical enzyme transistor, responsive to hydrogen peroxide was made by connecting two carbon band electrodes (～10 μm wide, 4.5 mm long separated by a 20-μm gap) with an anodically grown film of poly(aniline). Horseradish peroxidase (EC 1.11.1.7) was either adsorbed onto the poly(aniline) film or immobilized in an insulating poly(1,2-diaminobenzene) polymer grown electrochemically on top of the poly(aniline) film to complete the device. In the completed device, the conductivity of the poly(aniline) film changes from conducting (between - 0.05 and + 0.3 V vs SCE at pH 5) to insulating (>+0.3 V vs SCE at pH 5) on addition of hydrogen peroxide. The change in conductivity is brought about by oxidation of the poly(aniline) film by direct electrochemical communication between the enzyme and the conducting polymer. This was confirmed by measuring the potential of the poly(aniline) film during switching of the conductivity in the presence of hydrogen peroxide. The devices can be reused by rereducing the poly(aniline) electrochemically to a potential below +0.3 V vs SCE. A blind test showed that the device can be used to determine unknown concentrations of H(2)O(2) in solution and that, when used with hydrogen peroxide concentrations below 0.5 mmol dm(-)(3), the same device maybe reused several times. The possible development of devices of this type for use in applications requiring the measurement of low levels of hydrogen peroxide or horseradish peroxidase is discussed.     

高速列车车下设备模态匹配研究

建立了整备状态车体有限元模型及包含车体弹性的高速列车车辆刚柔耦合动力学模型,分析了车下设备吊挂方式对车体整备状态模态参数的影响,提出车下设备隔振橡胶件参数设计方法,并研究了整备状态下车体与车下设备悬挂模态参数的匹配关系。结果表明,车下设备采用弹性吊挂时,车体整备状态下的模态频率显著提升;合理设置车下设备隔振悬挂参数可有效降低车体弹性振动,算例中,当橡胶件的静挠度设置为8~9 mm时,设备浮沉频率可与车体垂向一阶弯曲频率避开,侧滚频率可与车体菱形变形模态频率避开,有源设备高频振动减振效果理想,车辆可以获得优良的运行平稳性,同时车下设备自身振动亦不剧烈。     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.