Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $hbox{TaN/HfO}_{2}$ Gate Stack Structure

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO₂ gate stack is demonstrated for the first time. The devices of low threshold voltage V_TH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility mu_FE ~ 240 cm²/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO₂ gate dielectric with the effective oxide thickness of 5.12 nm.     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

ZnO transparent thin-film transistors with HfO/sub 2//Ta/sub 2/O/sub 5/ stacking gate dielectrics

The performance improvement of ZnO thin-film transistors (TFTs) using HfO₂/Ta₂O₅ stacked gate dielectrics was demonstrated. The ZnO TFTs exhibited transistor behaviour over the range 0-10 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm² V^-1 s^-1, 0.5 V/decade and ~10⁶, respectively.     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Studies of yttrium oxide films prepared by RF magnetron sputtering

Films of yttrium oxide (Y₂O₃) were deposited on Si substrates from a Y₂O₃ target by RF magnetron sputtering. MIS capacitors in the form of Al and Y₂O₃ (400 Å)-Si were then fabricated. The leakage current density was about 10^-6 A/cm² at 1.3×10⁶ V/cm, and the breakdown field of the films was about 2.75×10⁶ V/cm. The dielectric constant of the sputtered Y₂O₃ was found to be about 12-12.7     

Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $kappa$ LTPS-TFT

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO₂ low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I_min is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO₂ gate dielectric and fluorine preimplantation can simultaneously achieve low V_TH ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high I_ON/I_min current ratio ~1.98 times 10⁷.     

ZnO-Based Fairly Pure Ultraviolet Light-Emitting Diodes With a Low Operation Voltage

A ZnO-based metal-insulator (HfO₂) -semiconductor diode was synthesized on a commercially available n⁺-GaN/sapphire substrate using a radio-frequency magnetron sputtering system. Electroluminescence measurements revealed that the diode exhibited fairly pure ultraviolet (UV) emission peaking at ~ 370 nm with a line width of less than 8 nm. By choosing a proper thickness of the insulator HfO₂ layer, the threshold voltage of the emission could be reduced to 2 V, demonstrating that this ZnO-based fairly pure UV light-emitting diode can be driven by two ordinary dry batteries. The reason for low threshold voltage is proposed in terms of the n⁺-GaN/sapphire substrate and the high-k insulator HfO₂ layer.     

A high performance MIM capacitor using HfO2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO₂ high-κ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (~200°C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO₂ MIM capacitor can provide a higher capacitance density than Si₃N₄ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2×10^-9 A/cm² at 3 V is achieved. All of these make the HfO ₂ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications     

300 GHz InP/GaAsSb/InP double HBTs with high current capability andBVCEO>6 V

We report MOCVD-grown NpN InP/GaAsSb/InP abrupt double heterojunction bipolar transistors (DHBTs) with simultaneous values of f _T and f_MAX as high as 300 GHz for J_C=410 kA/cm² at V_CE=1.8 V. The devices maintain outstanding dynamic performances over a wide range of biases including the saturation mode. In this material system the p+ GaAsSb base conduction band edge lies 0.10-0.15 eV above the InP collector conduction band, thus favoring the use of nongraded base-collector designs without the current blocking effect found in conventional InP/GaInAs-based DHBTs. The 2000 Å InP collector provides good breakdown voltages of BV_CEO=6 V and a small collector signal delay of ~0.23 ps. Thinner 1500 Å collectors allow operation at still higher currents with f_T>200 GHz at J_C=650 kA/cm²     

Power performance of InP-based single and double heterojunctionbipolar transistors

The microwave and power performance of fabricated InP-based single and double heterojunction bipolar transistors (HBTs) is presented. The single heterojunction bipolar transistors (SHBTs), which had a 5000 Å InGaAs collector, had BV_CEO of 7.2 V and J_Cmax of 2×10⁵ A/cm². The resulting HBTs with 2×10 μm² emitters produced up to 1.1 mW/μm2 at 8 GHz with efficiencies over 30%. Double heterojunction bipolar transistors (DHBTs) with a 3000-Å InP collector had a BV_CEO of 9 V and J_{c max} of 1.1×10⁵ A/cm², resulting in power densities up to 1.9 mW/μm² at 8 GHz and a peak efficiency of 46%. Similar DHBTs with a 6000 Å InP collector had a higher BV_CEO of 18 V, but the J _{c max} decreased to 0.4×10⁵ A/cm² due to current blocking at the base-collector junction. Although the 6000 Å InP collector provided higher f_max and gain than the 3000 Å collector, the lower J_{c max} reduced its maximum power density below that of the SHBT wafer. The impact on power performance of various device characteristics, such as knee voltage, breakdown voltage, and maximum current density, are analyzed and discussed     

Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

Hole injection SiO2 breakdown model for very low voltagelifetime extrapolation

In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 Å and 130 Å, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q_BD and t_BD behavior including a fluence in excess of 10⁷ C/cm² at an oxide voltage of 2.4 V for a 25 Å oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

High-performance self-aligned (Al,Ga)As/(In,Ga)As pseudomorphicHIGFETs

Transconductance as high as 676 mS/mm at 300 K was observed to 0.7×10-μm² n-channel devices (HIGFETs) made on epilayers with Al_0.3Ga_0.7As insulator thickness of 200 Å and In_0.15Ga_0.85As channel thickness of 150 Å. An FET K value (K=W_g Uε/2aL_g) as large as 10.6 mA/V ² was also measured from another device with transconductance of 411 mS/mm. The high K values are achieved under normal FET operation without hole-injection or drain-avalanche breakdown effects. These results demonstrate the promise of pseudomorphic (Al,Ga)As/(In,Ga)As HIGFETs for high-performance circuit applications     

Electrical characteristics of high-quality sub-25-Å oxidesgrown by ultraviolet ozone exposure at low temperature

We have developed a method for controllably and reproducibly growing self-limiting ultrathin oxides with excellent electrical properties in the range ~10-25 Å thick at temperatures ranging from 25 to 600°C, respectively, using an ultraviolet ozone (UVO₃) oxidation process. The self-limiting thickness depends primarily on the substrate temperature, allowing ultrathin oxide growth with precision and reproducibility using this UVO₃ process. Oxides grown by this method are comparable in electrical quality to thermal oxides, with similar leakage current densities and breakdown fields E_BD>10 MV/cm. Current-voltage (I-V) analysis shows oxide thickness uniformity to within 1% from center to edge of a 4-in wafer. Capacitance-voltage (C-V) characterization of ~25 Å oxides shows excellent saturation behaviour, with low midgap interface trap densities and no hysteresis or dispersion     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.